For an increasing number of designs, companies are finding it beneficial to design their own ASICs with system-on-a- chip (SoC) complexity. For reasons of cost reduction, quality improvement, IP protection and security, a full turn-key ASIC can be achieved for $1-5 million, particularly if the design can be built using mature technology nodes.
To further explore this topic, we asked questions from three leading experts in the field. Participating in the Q&A are:
• Michel Villemain, CEO, Presto Engineering, Inc.
• Guillaume Etorre, VP Engineering, Devialet
• Venkata Simhadri, CEO, Gigacom Semiconductor
Q: What is the decision-making process for deter- mining which applications are best addressed with an ASIC vs standard, off-the-shelf components? How does one calculate non-recurring engineering (NRE) costs, for example, and how does the anticipated part volume impact the decision?
Etorre: In many cases, particularly for IoT or other space-constrained designs, going with multiple standard compo- nents is simply not an option. A single chip must embed the microcon- trollers, sensors, battery management system, radios, etc. required by the application, in the smallest possible form factor.
When space is available, a standard component approach can be more appropriate to meet tight deadlines or to address situations where demand for the product is unproven. It can also serve as a stop-gap to serve the market immediately while a lower-cost ASIC solution is being designed.
If demand for the product is proven, a net present value calculation over a range of scenarios (best, typ., worst case for volumes and schedule for instance) will provide guidance on the best approach. An ASIC typically carries higher NRE (design, tapeout, qualification, test) but yields lower unit cost than an off-the-shelf solution. Depending on anticipated volumes and cost of capital, the lower unit cost of an ASIC will outweigh the higher NRE.
Simhadri: Primarily two factors can impact a company’s decision to design its own ASIC.
1. Competitive advantage – If the company is building its system using off-the- shelf components, competition can quickly reproduce it and you are only left with software as the differentiating factor. In this situation, you must have your own ASIC to protect your IP.
2. Cost – When addressing large volume markets the unit cost becomes an important factor and the only way to cut down the cost is to integrate/optimize the off-the-shelf components.
The typical NRE cost includes the cost of design, proto- typing (shuttle) and qualifying the part. Companies typically use a few benchmarks to justify the upfront cost.
For example, NRE cost is primarily dependent on the infrastructure (staff and tools) the customer already has in place. If the company already has a design team, EDA tools, etc. then the incremental cost might not be too high. However, without a design infrastructure already in place, it’s going to be a lot more time- consuming and costly. In this case, it is much easier to work with an ASIC design house to have all the infra- structure and some of the building blocks put in place.
Villemain: NRE is somewhat challenging to calculate since the duration of the project is often underestimated and unpredicted issues (who really does anticipate them!) bring additional cost to such a project. One way of mitigating this is to use external sources provided on (primarily) fixed- cost engagements. Beside ROI on NRE (function of margins and volume, indeed), drivers for using ASICs include: form factor, reliability, IP, power consumption and security.
Q: What are the tools and supply chain partners needed to successfully design an ASIC solution, including EDA software, foundry, packaging and test house?
Simhadri: You need the standard EDA tools for both Analog/ Digital, if you are designing a mixed-signal chip. Typically, you will have to work with at least two EDA vendors, such as Synopsys, Cadence, or Mentor Graphics. Many of the foundries will also work with small companies, provided you show a path to volume. However, in terms of design support (pdks, libraries, etc) foundries with better design infrastructure can save significant time. If you are a start-up or doing it for the first time, it can be quite daunting to setup the relationships and you can lose quite a bit of time to get the process going. But there are ways to save time and cost by outsourcing some of the work to the right design companies and echo system partners.
Villemain: Success is a function of a combination of multiple competencies that need to work coher- ently throughout the life of the product, especially post-design: industrialization, supplier management, quality, planning, logistics and product sustaining. This typically represents more than ten different skillsets that need to be part of the extended product team.
Etorre:
• Availability of proven IP (CPU, peripherals, interconnects, digital & analog I/O,…) for the chosen technology node.
• Affordable EDA software, with specific packages for companies designing only one or two chips at any given time, for specific end-user products vs. fabless IC companies which can spread the EDA license cost over many different chip designs every year.
• Efficient turn-key supply chain partner that can abstract out the complexity of foundry, packaging, test, storage and logistics for companies that lack critical mass.
Q: With the rise of IoT, IIoT and wearables, there’s much interest in analog/mixed-signal ASICs. How are their requirements different from traditional digital designs?
Villemain: Analog/RF designs tend to be smaller in size and to require less aggressive wafer fab processes. From a design standpoint, they demand less expensive EDA tools and less costly verification. However, their characterization and test is typically more complex and requires more expertise than a purely digital equivalent. Finally, yield management can be more demanding as the equation design window vs. process window is left more to the engineers than digital products, which can use semi-automated tools.
Simhadri: The primary difference in the require- ments is power and connectivity. If the ASICs must be connected to the internet, determining which protocols you need to incorporate on to the chip makes a big difference. Power is going to be a huge differentiating factor for the wearables, and designers are looking at various power saving techniques in an effort to optimize the power. Also, the foundries are offering special process nodes like SOI to address these markets.
In addition to the standard low power techniques like voltage islands and power shut off modes, the ASIC can further optimize the power by custom- izing the IP blocks for the specific applications. For, example, serial interfaces that burn lot of power, can be optimized.
Etorre:
• Design cycle is longer for analog IP than for digital.
• It is therefore critical to choose a foundry and a node for which all or most of the required IP are available.
•Analog IP is typically not portable between foundries or between nodes without significant rework.• •Custom analog IP is therefore a significant investment that will be depreciated if a foundry change or node change is required.
• The best nodes for analog, MEMS, RF, high- voltage and digital are usually not the same.
• Selecting the most appropriate node for the applications is not a trivial task.
• Introducing new functionality in a subse- quent version of an ASIC can require a node change and therefore major redesign of analog / mixed signal circuits. Anticipating future requirements can help make better technology choices.
Q: How do mask set costs of more mature technologies (180-40nm node) compare with those of 28nm and below, and how do mask costs enter into the overall cost equation?
Simhadri: I strongly advise our customers to use shuttles to prototype the ASIC and completely qualify it before spending a huge amount on the full mask. As expected, the 180-40nm shuttle costs are signifi- cantly lower than 28/16nm.
Villemain: With verification being less of a factor for analog/RF designs, mask sets can become a significant part of NRE below 90nm. Process technology is obviously a leading factor, but in addition, process routes can be costly because of additional options or IP, implying the addition of a mask/process layer, and thus, decreasing ROI in smaller geometries. Also, cost plateaus do exist (depending on the foundries) due to equipment transition (wafer size, lithography technol- ogies, etc.)
Etorre: The mask cost ratio between older technol- ogies and more recent ones can reach 20:1. For a 180nm design, once design, qualification and test fixtures are factored in, mask cost is not a significant contributor to the overall NRE.
Q: Out of the various advantages of ASIC design — cost reduction, quality improvement, IP protection and security – how would you rank their importance. Are there other advantages to ASIC solutions?
Villemain: What we see in the industry is a combi- nation of those factors (cost reduction, quality to architect an ASIC that replaces the discrete compo- nents in the system, which can reduce the BOM improvement, IP protection and security) as a function of the market our customers are operating in. The most common drive is, of course, that of cost (ASICs usually bring a dramatic product cost reduction), although for infrastructure applications, reliability is a key criterion, while for battery-operated applica- tions, power consumption reduction is mandatory— and all are benefits of using an ASIC.
In addition, more and more IoT segments require security in order to be even just a contender in the market, and an ASIC-based solution offers both a certifiable source of design and a cost benefit as compared to standalone secured elements.
Finally, in very competitive markets, the IP differen- tiation that an ASIC provides is a huge benefit.
Simhadri: IP protection and security shall rank first, followed by cost reduction. In some cases, off-the-shelf chips may not meet the performance requirements.
Etorre:
1. Real estate savings – an ASIC-based design is much smaller than an off-the-shelf approach;
2. Cost reduction
3. IP protection
4. Quality improvement, if any – combining various
functions and technologies (analog, digital, RF, power, MEMS, etc.) on the same die can lead to lesser quality.
Q: How has your company benefitted from an ASIC approach?
Etorre: Devialet’s Analog-Digital Hybrid (ADH) audio amplification technology was first implemented with discrete components. This discrete design is used in our high-end Expert Pro amplifiers and it supports the widest range of operating conditions.
In our Phantom speakers, we had to fit the same technology is a much smaller area. We specialized the analog circuit for the specific speaker drivers used in the Phantom and we designed an ASIC to deal with the analog part of the ADH technology.
Simhadri: Gigacom has been working with a company in the industrial IoT space and building systems for sensing gases and air quality. We have worked together by 10x and reduce the area and power significantly at the same time.
Q: How has the supply chain evolved to meet this new kind of demand?
Villemain: The supply chain needs to evolve in order to focus more on the backend than the frontend. If SoC brought RFCMOS to mass adoption with connected product, IoT, relying on a sensor-specific package, must integrate a companion ASIC driver and a transceiver; System in Package back-end technologies are gaining tremendous momentum. More and more companies will design their own ASICs, on well-proven, stable fab processes. However, packaging, reliability, test and security will become prime drivers, defining not only product costs, but also the ability to ramp, yield and scale up in volume. Supply chains (and especially the management of supply chains) is evolving accordingly.
For example, until recently, building an ASIC for an IoT device required the assembly of a team of experts, each with expertise in a different part of the process. The design might be created in-house or through an outside firm, and large companies, like automotive manufacturers, might assemble whole organizations, often called “operations” departments, with the sole task of managing the production of the specialized devices they needed. For a small company, with a game-changing new product idea, the cost and delay of assembling such a team can be fatal. If a competitor beats you to market you might not get a second chance. This need for manufacturing expertise led to the creation of “outsourced operations” companies, like Presto Engineering, that can manage the entire semiconductor manufacturing process from the completion of the design to the delivery of the tested product. By reducing the risk, cost, and difficulty of the production process, companies, such as Presto, are playing a key role in accelerating the proliferation of application specific semiconductor solutions.
Etorre: By design, ASICs run in lower volumes that standard parts. The supply chain must adapt to deal with more customers running lower volumes. This creates an opportunity for companies providing turn-key supply chain services to bridge the gap between numerous mid-volume customers and tradi- tional foundries and packaging houses who only address the largest fabless IC vendors.
Simhadri: The supply chain needs some improve- ments in the following areas. The older process nodes from 180nm to 40nm have suddenly become popular for IoT applications. However, most of the PDKs and other collateral were developed for older EDA tool versions and they need to be updated. Also, most of the IP vendors are targeting their resources for developing the IP for the latest process nodes where they get the best returns on their investment. Some of this IP has to be ported back to enable the ASICs in older nodes.
Also, to bring up these ASICs, the industry needs good support for packaging and testing facilities and all the top vendors are focused on high volume and leading- edge ASICs. Companies like Presto can potentially fill the needs.
