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Leti, a research institute of CEA Tech, is marking its 50th anniversary this year during industry events and workshops in Grenoble, Tokyo, and Taipei and at both SEMICON West and IEDM 2017 in San Francisco.

Founded in 1967 as an electronics research division of the French Atomic Energy Commission, Leti evolved into a global leader in micro- and nanotechnologies tailoring differentiating applicative solutions.

Leti solutions target a wide variety of sectors, including sustainable transport systems, telecommunications, health, consumer electronics, energy, smart cities, defense and security and space. Leti has formed partnerships with world leaders of industry, such as IBM, Intel, Qualcomm and Applied Materials.

Among Leti’s 60 startups are Soitec and the company that became STMicroelectronics.

Leti miniaturization technologies in everyday life

Leti’s iconic low-power FD-SOI technology can be found in game consoles, GPS receivers, connected watches and many other everyday connected devices.  The institute’s accelerometer that automatically switches between portrait and landscape can now be found in millions of smartphones, along with Leti’s radio-frequency technologies. Leti also develops technology for health care, such as scanners and exoskeletons to increase quality of life for people affected with quadriplegia. Leti serves the defense and security industries with infrared technologies.

“Leti is an innovation institute,” said Marie Semeria, Leti’s CEO. “It is unique in the world because it embraces a broad diversity of technologies: CMOS, sensors, communication systems, packaging and 3D integration, power electronics, imaging, integrated circuits and many more. We will emphasize both Leti’s cultural of pioneering research and its technological strengths throughout this 50th anniversary year and on our redesigned website.”

Leti 50th anniversary worldwide events throughout the year

JUNE 28-29: FRANCE

Leti Innovation Days 

Leti and partners will discuss how microelectronics can make a difference in health care, address environmental concerns in a competitive world and help industrials and society embrace the digital revolution during its Leti Innovation Days, June 28-29, in Grenoble. Keynote sessions on June 28 will be followed on June 29 by an immersive exhibition packed with technology demonstrators, proof of concepts, a start-up corner and offering dynamic presentations on three routes to innovation in digital transformation, new frontiers in health care and electronics-driven environmental change. The institute will host a gala anniversary dinner event at Chateau de Sassenage.

OCTOBER: JAPAN & TAIWAN

Leti Day

Leti also will host one-day Leti Day events in Tokyo and Taiwan during the second week of October.

JULY & DECEMBER: USA

Leti Workshops

Anniversary-year events will conclude with workshops July 11 at SEMICON West in San Francisco and the International Electron Devices Meeting (IEDM 2017) Dec. 3 in San Francisco.

A coalition of leaders from the global tech, defense, and aerospace industries, led by the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC), today released a report identifying the key areas of scientific research needed to advance innovation in semiconductor technology and fulfill the promise of emerging technologies such as artificial intelligence (AI), the Internet of Things (IoT), and supercomputing. The report, titled Semiconductor Research Opportunities: An Industry Vision and Guide, also calls for robust government and industry investments in research to unlock new technologies beyond conventional, silicon-based semiconductors and to advance next-generation semiconductor manufacturing methods.

“Semiconductor technology is foundational to America’s innovation infrastructure and global technology leadership,” said John Neuffer, president and CEO of SIA, which represents U.S. leadership in semiconductor manufacturing, design, and research. “Our industry has pushed Moore’s Law to levels once unfathomable, enabling technologies that have driven economic growth and transformed society. Now, as it becomes increasingly challenging and costly to maintain the breakneck pace of putting more transistors on the same size of silicon real estate, industry, academia, and government must intensify research partnerships to explore new frontiers of semiconductor innovation and to foster the continued growth of emerging technologies. Taking swift action to implement the recommendations from the Vision report will help usher in a new era of semiconductor technology and keep America at the head of the class in technological advancement.”

Neuffer also noted concern in the tech, research, and academic communities about proposed cuts to basic scientific research outlined in the Trump Administration’s fiscal year 2018 budget blueprint. Basic scientific research funded through agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), the Defense Advanced Research Projects Agency (DARPA), and the Department of Energy (DOE) Office of Science has yielded tremendous dividends, helping launch technologies that underpin America’s economic strength and global competiveness. The U.S. semiconductor industry invests about one-fifth of revenue each year in R&D – the highest share of any industry. Neuffer expressed the semiconductor industry’s readiness to work with the Administration and Congress to enact a budget that embraces the strategic importance of research investments to America’s continued economic and technological strength.

“Continued and predictable advancements in semiconductor technology have fueled the growth of many industries, including those historically based on mechanics such as automotive,” said Ken Hansen, president & CEO of SRC. “As the rate of dimensional scaling has slowed, the need to reinvigorate the investment in semiconductor research has become increasingly clear. Now is the time for industry, government, and academia to double down their resources and efforts to ensure the pace of renewal continues. Alternative strategies and techniques to the traditional scaling for performance are now being explored by SRC. Furthermore, with the support of SIA, SRC is building research programs that align with the Vision report, including complimentary technologies such as advanced packaging and communications. An infusion of funding is vital to expand the research breadth beyond the historical focus areas, enabling the industry to keep its promise of a continuous stream of products with improved performance at reduced cost. As industries look to future areas of growth and innovation, SIA and SRC are laying the groundwork for new discoveries through fundamental research.”

The Vision report is the culmination of work by a diverse group of industry experts and leaders, including chief technology officers at numerous leading semiconductor companies, who came together over a nine-month period in 2016-2017 to identify areas in which research is essential to progress. The report, which will be updated periodically moving forward, has active participation from the industry’s leading chip makers, fabless companies, IP providers, equipment and material suppliers, and research organizations. It will serve as a foundational guide for defining the semiconductor industry’s future research paths in 14 distinct but complimentary research areas. These areas, outlined in the Vision report, are as follows:

1. Advanced Devices, Materials, and Packaging2. Interconnect Technology and Architecture

3. Intelligent Memory and Storage

4. Power Management

5. Sensor and Communication Systems

6. Distributed Computing and Networking

7. Cognitive Computing

 8. Bio-Influenced Computing and Storage9. Advanced Architectures and Algorithms

10. Security and Privacy

11. Design Tools, Methodologies, and Test

12. Next-Generation Manufacturing Paradigm

13. Environmental Health and Safety: Materials and Processes

14. Innovative Metrology and Characterization

 

aicha-evans_1Intel Corporation today announced the appointment of Aicha S. Evans as chief strategy officer, effective immediately. She will be responsible for driving Intel’s long-term strategy to transform from a PC-centric company to a data-centric company, as well as leading rapid decision making and company-wide execution of the strategy.

“Aicha is an industry visionary who will help our senior management team and the board of directors focus on what’s next for Intel,” Intel CEO Brian Krzanich said. “Her new role reflects her strong strategic leadership across Intel’s business, most importantly in 5G and other communications technology. Her invaluable expertise will contribute to the company’s long-term strategy and product portfolio.”

“I look forward to working across the company to advance Intel’s ongoing transformation,” Evans said. “We have an exciting future ahead us.”

Evans is an Intel senior vice president and has been responsible for wireless communications for the past nine years. Most recently, she was the general manager of the Communication and Devices Group. Evans joined Intel in 2006 and is based in Santa Clara, Calif. In her new role, she will report to Intel CFO Bob Swan.

An internal and external search is underway for a new general manager of Intel’s Communication and Devices Group.

Ultratech, Inc. (Nasdaq: UTEK), a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HBLEDs), as well as atomic layer deposition (ALD) systems, today announced that it has received follow-on, multiple system orders from several outsourced semiconductor assembly and test (OSAT) companies in Taiwan, Korea and China. The AP300E lithography stepper will be used for leading-edge copper pillar and wafer-level packaging (WLP) in high-volume manufacturing (HVM). Ultratech plans to begin shipping the systems in Q2 and Q3 of this year.

Ultratech General Manager and Vice President of Lithography Products Rezwan Lateef stated, “OSATs are rapidly expanding their advanced packaging capabilities to capture the strong demand for copper pillar and fan-out package solutions. These customers look to their equipment suppliers to provide highly reliable, flexible, extendible and cost-effective solutions coupled with excellent application-specific knowledge. The AP300E lithography stepper delivers on all these aspects coupled with outstanding regional support. Ultratech believes that success in the OSAT market requires local, on-site support and has greatly expanded its presence (both in personnel and infrastructure) in the Asia Pacific region with a focus on Taiwan, China and Korea. These repeat, multiple system orders across the broad OSAT spectrum are a clear validation of our market leadership position and a strong statement of continued partnership from our customers.  We look forward to working with these valued customers to meet their current production needs and to develop the applications of tomorrow.”

The AP300 family of lithography systems is built on Ultratech’s customizable Unity Platform, delivering superior overlay, resolution and side wall profile performance and enabling highly-automated and cost- effective manufacturing. These systems are particularly well suited for copper pillar, fan-out, through-silicon via (TSV) and silicon interposer applications. In addition, the platform has numerous application-specific product features to enable next-generation packaging techniques, such as Ultratech’s award winning dual-side alignment (DSA) system, utilized around the world in volume production.

ATTOPSEMI Technology, Ltd. today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program, to provide a scalable, non-volatile one-time programmable (OTP) memory IP to be compatible with GF’s 22FDX technology. ATTOPSEMI’s I-fuse OTP IP offers increased reliability, smaller cell size, low programming voltage/current, and high data security enabling customers and designers the ability to utilize an advanced OTP for harsh applications such as automotive, 3D IC, and IoT applications.

The opportunity for advanced OTP memory technology is greater than ever. As the volumes and technical demands increase for Internet of Things (IoT), processing performance grows and memory intensive applications advance, ATTOPSEMI’s I-fuse fills the need. Consumer, communications, automotive and wireless markets require smaller sizing, ease of programmability and high levels of reliability. With its patent-proven structure, the I-fuse can guarantee zero-program defect giving customers the needed knowledge of reliability and execution.

“ATTOPSEMI’s new offering should benefit our 22FDX customers in all the key market segments we address, especially for IoT and processor intensive applications,” said Alain Mutricy, senior vice president of product management at GF. “Their commitment continues to demonstrate strong industry interest in GF’s FDXcelerator program and the 22FDX value proposition.”

“We are excited to expand our engagements with GF and believe that our technology will help their customers deliver the functionality the market has been asking for,” said Chung Shine, Chairman, ATTOPSEMI. “We believe that our development has given us the ability to generate a smaller cell size and more reliability than our competitors along with a very scalable solution.”

ATTOPSEMI’s I-fuse is a fuse-based OTP technology that offers up to 100x reliability, 1/100 the cell size, and 1/10th the program current than traditional e-fuse technologies. Highlights of the I-fuse include:

  • Limited program current below a catastrophic breaking point
  • Use of junction diode, instead of MOS, as a program selector in an OTP cell
  • Smaller cell improving program efficiency enabling program current reduction

Ultratech, Inc. (Nasdaq: UTEK), a supplier of lithography, laser-processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HB-LEDs), as well as atomic layer deposition (ALD) systems, this week announced that two China foundries placed follow-on orders for laser spike anneal systems. Ultratech’s LSA101 laser spike anneal systems will be used for 40- and 28-nm production. The LSA101 dual-beam tools were chosen over competing systems due to greater flexibility and capability for annealing with low overall thermal budgets. Ultratech plans to ship the LSA101 tools to the customers’ foundries to China in Q1 2017.

The low cost of 28nm planar technology continues to drive growth and numerous foundries are ramping capacity expansion to take advantage of the optimal performance-to-cost ratio at this geometry. Foundries in Asia are leveraging the value proposition offered at the 28-nm node to meet the strong demand for low-cost chips for mobile devices. The LSA101 dual-beam system is designed for advanced applications, such as gate stack formation, silicide or post-silicide anneal to deliver leading technology in a cost-effective solution. Cost-driven foundries value Ultratech’s LSA101 systems due to the impressive flexibility to meet requirements for today’s volume production at 40-nm, 28-nm, and extendibility to 14-nm, 10-nm and below nodes.

“These follow-on orders strengthen our dominant position for advanced millisecond anneal within the foundry market in China,” said Jim McWhirter, Ph.D., vice president and senior scientist, laser technology at Ultratech. “While we are currently working with these customers to ramp capacity for 40- and 28-nms, the LSA101 system has demonstrated extendibility for advanced FinFET nodes. As a result, building on our long-term relationships, we can effectively work with our customers using our LSA systems to support their planer device applications today with extendibility for their future FinFET device roadmaps. Ultratech’s product focus remains targeted at meeting customer requirements for their advanced millisecond annealing applications.”

ULVAC, Inc. is pleased to announce the NA-1500 dry etching system for 600mm advanced packaging substrates, providing for uniform Descum and Ti etching processes.

Low_ulvac1

Higher data transfer speeds require higher-density packaging technologies, while advanced mobile and wireless devices require thinner and higher-pin-count IC packages. Fan-Out Wafer Level Packaging (FO-WLP) is widespread, while Panel Level Packaging increases substrate size from 300mm to 600mm.

While there are many 200mm/300mm wafer dry etching systems in the market today, there was no dry etching system for 600mm substrates, providing for a uniform Descum process and Ti etching process. ULVAC developed the new system to address this need, and support mass-produced packaging processes.

The new NA-1500 dry etching system is made possible by enhancing our proven plasma source. Our plasma source enables fast, low-temperature etching in the resin layer, which had been previously impossible with existing CCP methods.

Our plasma source is also applicable to fluorine gases, so seed layer Ti etching, which requires a wet process, can proceed without side etching. SiO2 and SiN etching is available on the NA-1500 as well.

The NA-1500 dry etching system provides stable transfer and processes without abnormal discharge, ensuring warpage from the enlarged substrate is never an issue.

Intel Corporation today announced that Omar Ishrak and Greg Smith have been elected to Intel’s board of directors.

“We are very pleased to welcome two new, independent directors with the depth of leadership experience at innovative, global companies that both Mr. Ishrak and Mr. Smith bring,” said Intel Chairman Andy Bryant. “We look forward to their valuable contributions as Intel continues to transform itself for growth in emerging, adjacent market segments.”

Omar-IshrakIshrak, 61, is the chairman and chief executive officer of Medtronic, a global leader in medical technology. He has served in that role since 2011. Prior to joining Medtronic, he spent 16 years in various roles with General Electric Company, most recently as president and chief executive officer of GE Healthcare Systems, a division of GE Healthcare. He is a member of the board of trustees of the Asia Society, which promotes mutual understanding and strengthening partnerships among peoples, leaders and institutions of Asia and the United States in a global context, and a member of the board of directors for Minnesota Public Radio.

Smith, 50, is the chief financial officer and executive vice president of corporate development and strategy at Boeing, the world’s largest aerospace and defense company. He has served as Boeing’s finance leader since 2012 and its strategy leader since 2015. Previously, Smith held various leadership roles across Boeing’s finance function and operations. He rejoined Boeing in 2008 after serving for four years as vice president of global investor relations at Raytheon. Smith serves on the board of trustees for the Chicago Museum of Science and Industry, and the board of directors of the Economic Club of Chicago, the Chicago Botanic Garden and the Northwestern Medicine Community Physicians Group.

Microsemi Corporation (Nasdaq: MSCC), a provider of semiconductor solutions, today announced the planned closure of its manufacturing facility in China. Focused on lower value discrete solutions, the devices manufactured at the facility are not aligned with Microsemi’s strategic direction, and company resources will be invested elsewhere in higher value, higher growth products and end markets. Customers have been notified and the process of closure is under way. The company reports that no material impact on earnings for the company is expected due to this closure.

Microsemi Corporation (Nasdaq:  MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets, and is headquartered in Aliso Viejo, California. The company employs approximately 4,800 workers globally.

At the SEMI Industry Strategy Symposium in Munich, SEMI announced recipients of the European SEMI Award for 2016: Rolf Aschenbrenner, deputy director of the Fraunhofer IZM; Eric Beyne, fellow and program director of 3D System Integration at imec; and Gilles Poupon, CEA fellow on advanced packaging and 3D integration at CEA-Leti. Since 1989, the European SEMI Award has been presented for significant contributions to the European semiconductor and related industries.  The three winners were nominated and selected by peers within the international semiconductor community in recognition of outstanding contributions in the field of 3D Integration.

“While the industry recognizes that SEMI Members imec, Fraunhofer and CEA-Leti are leaders in packaging technologies, the contributions of Rolf Aschenbrenner, Eric Beyne and Gilles Poupon and their teams are groundbreaking and advanced the semiconductor industry,” says SEMI Europe president Laith Altimime.

Rolf Aschenbrenner received a B.Sc. in mechanical engineering in 1986 and an M.Sc. in physics in 1991 from the University of Giessen. In 1994, he joined the Fraunhofer Institute for Reliability and Micro-integration in Berlin (IZM), where he is presently head of the department for chip interconnection technologies, and deputy director of the institute. Rolf Aschenbrenner’s research work spans from manufacturing process fundamentals to applied manufacturing problems. He has made substantial research contributions in thin and flexible electronic assemblies, end the development and analysis of innovative process technologies for all aspects of system level packaging. He served on various committees, and in 2013 he received the IEEE CPMT David Feldman Award.

Eric Beyne obtained a degree in electrical engineering in 1983 and a Ph.D. in Applied Science in 1990, both from the Catholic University Leuven. Since 1986, he has been employed at imec, where he works on advanced packaging and interconnect technologies. Currently, he is imec Fellow and programme director of imec’s 3D-integration programme. For more than ten years, Eric Beyne has been a pioneer in 3D system integration. He is a strong believer in the building of ecosystems in packaging and 3D, and has catalysed cooperation between IC-makers, designers, and Materials and equipment makers.

Gilles Poupon was educated at the University of Grenoble and the Conservatoire National des Arts et Métiers in Paris, where he received an M.Sc. in electrochemistry in 1985. He joined CEA-Leti in Grenoble in 1987. He became manager of the High Density Interconnect and Packaging Laboratory at Leti, where he was involved in the development of flip-chip technology, MEMS packaging and 3D-integration. Currently, he is programme manager on Advanced Packaging at CEA-Leti. Poupon is also a scientific advisor of the Eureka Initiative for Packaging and Integration of Microdevices and Smart Systems, and a member of various other committees involved in packaging and 3-D integration.

The European SEMI Award was established almost three decades ago to recognize individuals and teams who have made a significant contribution to the European semiconductor and related industries. Prior award recipients hailed from these companies: EV Group, Infineon, Semilab, Deutsche Solar, STMicroelectronics, imec, Fraunhofer Institute, and more.