A decidedly non-technical term was in vogue this week at the very technical 25th European Photovoltaic Solar Energy Conference (EUPVSEC). The term “bankability” was often used to describe the likelihood of success of a given technology. In these days of scarce capital, the only projects that will be funded are those that banks and insurers have deemed to be fund-worthy (outside of China anyway). “Banks demand extensive performance and reliability data before funding major installations,” noted one presenter from Applied Materials, claiming that this was “critical for market penetration of a new PV technology.” This particular presenter was discussing the merits of thin film PV tech, but crystalline PV suppliers were making similar arguments regarding the bankability of their own technology, which is arguably more proven and certainly more mainstream.

How this will play out is anybody’s guess, since long-term reliability is somewhat of a guessing game based on an extrapolation of models and limited field tests, particularly when it comes to new materials. Almost all PV module suppliers offer 20-25 year warranties but nobody really knows how panels will withstand the test of time. Corrosion can creep in, plastics can yellow, dopants can move and electromigration can lead to increases in line resistance. Many PV proponents believe solar farms being installed today will live on in perpetuity, since the world will always need power and the sun will always shine, but materials do tend to wear out.

Maybe bankers can intuit the viability of given technology better than expert physicists, but I suspect their questions of bankability will only be answered by reams and reams of data which they are ill-prepared to decipher.

The one and only driving factor in the photovoltaics industry is cost per Watt. This is primarily a function of efficiency – how much of the sun’s power is converted to electricity — and the cost of manufacturing and installation. The ultimate goal of course is to achieve grid parity, where the cost of producing power with PV is the same or better than that achieved by traditional means (coal, hydro, nuclear, natural gas, etc.). That’s Fact #1 (with the obvious exceptions of odd applications such as PV in outerspace and on ladies’ handbags).

Fact #2 is that today’s PV boon is artificially driven by feed in tariffs, tax incentives, politics, unlike “real” market boons such as high brightness LED lighting. It is ironic that the 25th European Photovoltaic Solar Energy Conference (EUPVSEC) is being held in Spain, which just recently renounced FiTs after accruing billions of euros of debt (too much subsidized PV was brought on-line too quickly).

Fact #2 is of little long term significance, however, since billions of dollars (and euros) are being spent to advance PV technology, ultimately bringing about grid parity. This creates a real market for PV and eliminates CO2 emissions, thereby saving the world.

Fact #3 is that China is dominating the photovoltaics manufacturing business. Companies in China are able to manufacture photovoltaics more cost effectively than anywhere in the world, and by all accounts are also implementing new technologies very quickly and effectively. Never mind that their costs are low because they are able to feed energy-hungry manufacturing operations with cheap CO2-belching coal-fired power plants. Surely the CO2 reductions in Europe made possible by PV more than offset the increase in CO2 from China!? No? Well, I said never mind.

The Ten Million Solar Roofs Act of 2010 (S. 3460) was was passed by the Energy and Natural Resources Committee by a vote of 13 to 10 on July 21, 2010. It was introduced by Sen. Bernie Sanders, a member of the Senate energy and environment committees and chairman of the green jobs subcommittee.

The bill sets a goal, to be met through this and other incentive and R&D programs, of installing solar electric or water hearing systems on at least 10 million properties in ten years.

It provides competitive grants through Department of Energy for Fiscal Years 2012-2021, starting with an authorization of $250 million for Fiscal Year 2012. The Department of Energy is directed to provide Congress with a report on recommendations for achieving the ten million solar goal including how to best leverage funds through S. 3460 for Fiscal Years 2013-2021 (those years have an open authorization to provide flexibility to respond to the Department’s recommendations).

Competitive grants to states, tribes, cities, towns, and counties to help them establish or expand solar loan and incentive programs for homeowners, businesses, schools, and other entities. This approach ensures compatibility with existing incentive programs.

Solar systems of 1 megawatt (or thermal equivalent) or less are eligible. No homeowner, business, or school can receive federal/state/local incentives worth more than 50 percent of the cost to purchase and install a solar system (excludes loan programs). 20 percent non-federal cost share. Grantees submit to the Department of Energy an implementation plan including how many solar systems they will deploy under the grant, and how many participants will receive incentives or loans. They will certify that grant funds will be used to establish new programs or supplement, but not supplant, existing solar funding.

Criteria for the grants include ensuring geographic and population size diversity among awardees, and a ensuring a minimum (at least 2 percent of funding) is available to tribes. Preference is also given to grant recipients who have, or will commit to establishing, net metering, interconnection, and other solar access rules consistent with their authorities.

Increasingly, we are hearing about consolidation in the semiconductor industry. Bill McClean of IC Insights has perhaps pointed this out most clearly, noting that the top 10 capacity leaders held about 60% of the total 2009 worldwide IC capacity, and the top 15% held a 71% share. Looking at only 300mm capacity, the consolidation is even more obvious: the top 10 leaders held an imposing 84% share with the top 15 companies holding all but 8% of the world’s 300mm IC fabrication capacity, according to McClean.

This is good news for those 15 companies, but not such good news for consumers. “With so few companies representing such a large share of the leading-edge IC production, IC Insights’ long-held belief that the companies left standing after the ‘shakeout’ will reap the rewards of increased profitability, is now coming true. However, for the IC user, this also means that IC average selling prices are unlikely to decline as they have in the past. The pricing pendulum is now swinging in favor of the IC producers and it may not be swinging back for a long time,” McClean said.

With a greater percentage of spending coming from a shrinking number of companies, semiconductor industry capital spending is becoming more concentrated. Because of this trend, IC industry capacity is also becoming more "concentrated." As tight as overall IC capacity has been in the IC industry since the first half of 2009, 300mm capacity has been even tighter, McClean notes. In 1Q10, 300mm capacity utilization was 97%, which is essentially indicate a "sold out" situation.

With most capital spending in 2010 going toward developing and moving to finer feature sizes (with little going toward adding wafer starts), the availability — or lack of availability — of IC devices will become a major factor in the second half of this year. Ion fact, IC Insights believes that one limiting factor to 30% or greater IC market growth in 2010 might be the lack of IC fabrication capacity needed to support such growth.

Also expect higher average selling prices (ASPs) for almost all types of ICs. “Given that almost all DRAM, NAND flash memory, and microprocessors are produced using 300mm wafers, it follows that each of these segments registered increasing average selling prices throughout 2009 and into 2010,” McClean said. “IC Insights believes that buyers of these IC devices should be prepared for similar ASP trends for these products in the second half of this year.”

While all of this is going on – the consolidation, sold-out capacity and higher selling prices for mainstream ICs – I keep thinking about applications that fall outside of the mainstream. Where are those apps that require different types of equipment and materials technology and different process technology? Do they exist? How big of a market do they represent? Might they be a way for suppliers to diversify outside of the mainstream 15-companies-now-controlling-the-spending semiconductor industry?

My list of applications that offer a potential way to diversify for companies offering thin film deposition and patterning capabilities include: MEMS, hard disks and read-write heads, flat panel displays, optical disks, photovoltaics, LEDs, CMOS image sensors, and superconductors. The MEMS market is perhaps the most intriguing of these since it encompasses so many different types of devices, from microphones to sensors to micro-fluidic labs on a chip.

But perhaps the application with most explosive potential is intelligent medicine. Imagine taking a digestable “smart” pill that is in essence an integrated circuit. As that pill works it’s way through your body, it monitors the status of all kinds of functions and reports the results to your iphone or similar device. That kind of technology is, in fact, already here. Proteus BioBed in Redwood City, CA has developed what it call the Raisinâ??¢ System (there was an Apple on your desk, a Blackberry on your belt and now a raisin inside, quips Proteus CEO Andrew Thompson). The initial application of the Raisin System is for the treatment of patients with heart failure. The system senses and records the precise time a patient takes one or more microchip-enabled drugs, providing physiologic feedback and decision-support to the patient, caregivers and clinicians, thus facilitating a cost-effective pathway to improved patient outcomes through personalized medicine.

How cool is that!? It doesn’t take much imagination to envision all kinds of medical devices with new and unique requirements that could leverage traditional IC manufacturing technology. This market could be huge, given the aging baby boomer population and over-loaded healthcare system. Consolidation? Who cares? Bring on the new apps!

In the January issue of Solid State Technology, I wrote about life after the "reset" button and how the lack of R&D funding could well bring an end to Moore’s Law.

That very issue was one of the key "take aways" from last week’s ISS. What I heard from a variety of speakers is this:

A massive restructuring is underway that will leave only a handful of companies producing devices at the leading edge. Bob Johnson, VP of research at Gartner, predicts that by 2014 there will be only 10 companies operating at the leading edge: 1-2 nonmemory IDMs, 4-5 memory companies, and 3 foundries.

Hundreds of other companies will still be producing devices at somewhat larger dimensions, but the fragmentation is widening between those that can afford the most advanced-node technology, and those who can’t. "Those two segments are radically different and they’re going to get even more different," said Handel Jones, CEO of International Business Strategies, also speaking at the Industry Strategy Symposium. Despite that rift there’s still growth for those who choose not to push ahead to the advanced nodes. In fact, he expects to see capacity shortages for some of these lagging feature dimensions in the next few years.

Johnson described several economic forces at work that could derail Moore’s Law due to lack of R&D funding. One factor is the number of major IDMs that are moving from a full manufacturing position to an asset-light or fabless position. “The number of companies that are actually participating in the leading edge is shrinking,” Johnson said. “If you look forward about five years, you come to the very realistic assumption that there are going to be at most 10 companies doing leading edge manufacturing. By leading edge, I mean the two most advanced process nodes. Right now, that would be 45nm and 32nm. By 2014, it would be 22nm and 15nm. How many of those companies will be operating at the absolute leading edge, in other words 15nm, by 2014? Just cut those numbers in half,” he said. “You’ve really got about five companies out there that are really going to be seriously considering manufacturing in accordance with the Moore’s Law pace.”

Jones also predicts significant changes over the next 5-10 years. By the time the 22nm generation rolls around in 2012, he predicts there will be only three IDMs: Intel, Samsung and STMicroelectronics, and in terms of foundries working at 22nm, he thinks TSMC and GobalFoundries (which recently acquired Chartered Semiconductor) will be around. The fate of Samsung, which recently entered the foundry business, will depend on the success of their model, he said, adding that SMIC is an unlikely participant, and the capacity of UMC is “unclear.”

A similar situation exists in the memory market. “What we see today is a number of companies in the DRAM, NAND flash and NOR flash businesses, but if you look out two to five years, you’re going to have one or two companies and that’s it,” Jones said. Samsung will again be a major player, with a projected 50% of the DRAM market and 60% of the NAND flash market. “What we see now is Samsung moving ahead very rapidly and the others falling behind. The gap is widening,” he said. Toshiba is a distant second, at least in NAND flash, where Jones expects them to garner 30% of the market.
Johnson said the higher costs of leading edge technology also means that companies must target only very large markets. At the 32nm mode, he said those markets needed to be about $2 billion. “The idea of being able to build a leading edge device that might target a $100 million market… those days are gone,” he said. “If we look at our current forecast and take it out to 2013, there are really only about five major markets that qualify for the greater than $2 billion TAM. That’s PCs, cell phones, video games, TVs and set-top boxes. That includes all the new things we’re seeing coming out of the CES show,” Johnson said.

Another trend that affects the ability of the equipment industry to fund R&D is capital intensity. Long term the trend in capital intensity—simply capital spending as a percent of revenue—has been declining, Johnson noted. In part, this is because people know how to build fabs more efficiently, but it’s also because the industry’s growth rate is declining. Once at 17% CAGR, Johnson said we’re realistically looking at a long term growth rate in the 5%-7% range. “It takes less capital to keep that going,” he said.

One of the main drivers behind this consolidation is price pressure. “The semiconductor industry, even though it’s recovering from a revenue perspective, is not healthy from a profit perspective,” Jones said. “Today, a relatively small number of semiconductor companies are making good profits. The market in 2010 will be comparable to the market in 2007 from a revenue perspective. Unit volumes though are up about 20-30%, so we’ve had an erosion of prices by 20%-30%. We’ve had some efficiency improvements but we’ve also seen a loss in gross profit margin and also a loss in operating income.”

Jones believes this will result in “a significant restructuring” in which “only the top two or three companies in specific markets will survive." The drive from 32nm to 28nm will force additional consolidation, he added.

A similar type of consolidation is seen on the front-end semiconductor manufacturing equipment front (less so on the back-end test and packaging side). Gartner’s Johnson said that equipment suppliers will have “lost” about $116 billion in revenue between 2007 and 2014 due to the recession and record low levels of capital expenditures. This equates to about $17.4 billion in lost R&D.

This is happening at the same time when R&D costs are escalating due to a demand for continued shrinks, more advanced device structures and even a move to 450mm wafers (which continues to be a hotly debated topic).

Many believe this consolidation and funding gap has the potential to stop Moore’s Law dead in its tracks, perhaps at the 22nm generation. Jones said that the benefits of scaling, which he measures in terms of cost per gate trend, are not what they once were. The move to 90nm achieved a big cost decline in cost per gate, in part due to the transition from 200mm to 300mm wafers and associated productivity gains, he said. The move to 65nm brought “a fairly reasonable” decline, and then a small decline with 45nm and 32nm transitions. With 22nm, however, he said there actually will be an increase in the cost per gate — and without a reduction in cost per gate, many will question the need to move to the small feature dimension. "When you look at what applications drive the technology, if it is low-power (such as for handsets), that’s a cost-driven market," Jones said. "Maybe going to a smaller dimensions will not give you the required payback.”

As a result of increasing costs, Jones also sees a reduction in the number of designs at advanced technology nodes. He said for a 28nm design, the costs can easily be in the $100M-150M range, and if you add software it can be up to $200M. “If you look at the normal metrics for R&D, you need 10× revenue from a production point of view. You then need $1.5 billion in revenue — and of course that happens in only a small number of products,” he said. “After 22nm, the technology gets even tougher. The two year cycle is fading fast.”

Bob Bruck, VP of Intel’s technology and manufacturing group and GM of technology manufacturing engineering, also spoke at ISS, adding that the number of fabs built each year has been declining: less than ten are expected to be built in 2011 and 2012, respectively (the majority of those being 300mm fabs). The cost of a fab is about $4B, a pilot line costs $1B-$2B, and an advanced R&D process team can cost $500M-$1B. “You’ve got to have a large TAM to support this kind of investment, and you’ve got to have a pretty good gross margin on the product base to support this kind of investment,” he said. "These types of dynamics are shaping this consolidation effect."

Johnson adds that "the guys that are making the chips" are facing an increasingly difficult decision: ‘Do I go with the leading edge or don’t I?’ He said we’ve been seeing the effects of that decision for some time. "Looking at the lag between when the first company beings producing at a given node – and of course that has always been Intel – and when 10% of the AASP design starts have occurred at the node. The 10% is a fairly arbitrary number but it indicates a fairly reasonable change for actually getting volume production happening at that node. At 130 nm, the industry was in lock-step. By 90/65 nm, we have a two year lag for the AASPs which largely determines foundry production to start getting their designs in behind the industry leaders. By 32 nm, we’re thinking that’s going to be a four year lag. If the foundry sweet spot, and the sweet spot of the AASPs and the ASICs that addresss some of the key consumer markets and mobile markets are actually be going to be running behind the leading edge. They’re not going to be leading edge when they start getting good volume," Johnson said.

Conclusion: Within five years, the ability of the industry to stand the traditional Moore’s Law technology curve will depend not upon the laws of physics. The real question is how do we pay for it and how to fund the necessary R&D to get there.

One bright spot: through-silicon vias (TSV) and 3D integration, which have the ability to increase functionality equivalent to a move to a new technology node. “In the past we were very cautious on TSV. We’ve become a lot more positive,” Jones said.

Acro Energy Technologies Corp., a leading U.S. solar integrator, announced yesterday that it has signed a Stock Purchase Agreement with Energy Efficiency Solar, Inc., a California corporation headquartered in Pomona, Calif. ("EE Solar") and Bill
Korthof, the sole shareholder of EE Solar.

EE Solar is a full-service solar energy company that has been installing residential and commercial solar systems in Los Angeles, Orange, and San Bernardino Counties since 1989. EE Solar generated approximately $4.2 million in revenue in 2008, servicing customers from its offices in Pomona and Orange. Korthof is the president of EE Solar and will join the Acro Energy team.

"Southern California is the largest growth market for distribute solar," said Nat Kreamer, President of Acro Energy. "Bill and the EE Solar team give Acro a strong platform for helping more southern Californians – who pay among the highest rates for electricity in the Country – save with solar."

Under the Purchase Agreement, Acro Energy will acquire all of the issued and outstanding shares of EE Solar for a purchase price of $1,500,000, consisting of
$250,000 cash, a promissory note in the amount of $750,000, and $500,000 of common stock issued from the treasury of the Company at a deemed price of CDN$0.24 per share. The company will also enter into an employment agreement with Korthof, as general manager, Pomona Operations.

I had the good fortune to catch up with Nat Kreamer yesterday before the deal was signed, and asked him what it was his customers were looking for in a PV system. In addition to being the interim President of Acro Energy Technologies and member of the Board of Directors, he was a founder, President, and Chief Operating Officer of SunRun, a leading provider of residential solar power purchase agreements. Kreamer has also worked in power industry consulting, clean energy investing, and energy trading. He graduated from Rice University and Northwestern University. An officer in the US Navy (Reserves), Kreamer is an Afghanistan war veteran and recipient of the Bronze Star Medal. He is a Senior Advisor at the Madison Policy Forum, which promotes non-partisan dialog about timely national security issues.

Here’s the Q&A with Kreamer:

Q: When you look at all the various elements of a PV system – the cells, inverters, cabling, trackers – where is the technology going and how aware are your customers of changes and how things are evolving? What are their main requirements?

A: Clearly we’ve seen a lot of upstream investment in the marketplace. In solar panel equipment/module manufacturers all the way to people like Spire who make the fab equipment. That has benefited the declining ASPs which really grows the addressable market of solar because it’s made it more affordable for people and more cost-competitive vis-à-vis power from the grid: the avoided cost of power. I think that general trend is very positive for the whole industry. In essence it will have a much larger industry and there will be more power generated from solar here in the United States and around the world.

There are a couple of things that an end customer thinks about. We think about it in two parts: We are an integration business at Acro, meaning we need to decide who we are going to have a relationship with from a manufacturer’s standpoint and what products we are going to install on customers roofs. Some of those customers pay us directly as cash so they’re the end consumer of the power and they also own the system. Other customers, such as SunRun, own the system and they sell electricity to the end customer. In both of those cases, clearly price is important because it needs to be economically valuable to go solar for the customer. Quality and reliability are very important. The level of service from the manufacturer is also important. You’ve got to have all three of those to be a contender with serious businesses in this industry. That can be a challenge for some of the more start-up organizations that you get in module manufacturing as well as the inverter space where you have complex, expensive pieces of equipment that are essential to the system and should have a long life. As a consequence I think end users tend to be less experimental with what they’re buying as equipment because they want to know they will get the power that they paid for, whether they are a buyer of capacity and consumer of that power or they’re a buyer of capacity and a reseller of electricity.

The one thing that you clearly see is that most manufacturers today are able to create a module on the silicon side that has enough Watts for it to work in nearly every application. So Watt-density or efficiency is less of an issue in the residential market than it would have been five or ten years ago. You infrequently can’t find 500 square feet on a residential customer’s home where you can put up panels. The second component is aesthetics are clearly important: people want to make sure they have something that looks good, but they want to make sure it’s really going to generate. Depending on where your customer is and what the application is that can be important. Lastly, I think that there is – if you think about it on the inverter side, that’s an area where we’re starting to see more innovation and more products come out whether it’s effectively charge controllers for PV systems that allow you to manage shading. We’ve seen some announcements of that here at the show. Or applications like nphase inverters which are micro-inverters that are panel-attached. Those are become more popular and fitting into the designs. Definitely popular to end customers in so much as monitoring capabilities have a stickiness factor to them especially in the retail marketplace that is very attractive. The tradeoff typically with those applications is they increase the installed cost/Watt so you have to balance that as what is my total cost based on this customer and what is the value.

The reality is there are two ‘greens’ in our business. The first green is cash: how much is this going to cost and how much am I going to save? The second green is ‘I feel good about doing this’. Any equipment that addresses t is the second green as their primary value proposition typically don’t do well vis-à-vis the ones that do a good job on the first value proposition.

Q: Some PV panels are manufactured in China using the most expensive materials possible. Even though they do offer guarantees of 20 years or 25 years, I would question the long-term reliability. Does that come up?

A: We have gone with market leaders as a company. Our panel suppliers are SunPower, Sharp and Sunteh. There are a lot of things that are available that can be at more competitive prices but to your point I don’t think it’s a balanced approach to providing value and reliability to get that power. If you pay 20% less for a panel and it generates for well over 7 years but then you find that half of your array is out, you may have chewed through all the savings in your value if you’re a retail customer. You’ve got to be careful about being penny-wise and pound foolish over the long term investment and we feel like we have very good relationships with as well as good options for our customers on all the dimensions of efficiency, aesthetics, reliability, strength of manufacturer warranty, historic performance. If you looked at any of those three suppliers, you’d be hard-pressed to say they’re not leaders. We’re also not speculating with technology that is untested or manufacturers that are untested.

The 55th International Electron Devices Meeting (IEDM) will be held next month, from December 7-9, at the Hilton Baltimore. One of the highlights of the year for us tech editors is when we receive the set of abstracts from the conference organizers, provided in advance so we can write our previews and plan our week at the conference.

The conference is well known as the place where all the major semiconductor manufacturers officially unveil the latest technology advances, where speed records are announced, and where some of the emerging, research-level types of devices are reported for the first time. This year’s emerging technology session will showcase graphene nanoelectronics, including how to integrate graphene into field-effect transistors, interconnects and other IC applications; graphene-based heterojunction devices that exhibit full quantum transport; spin transport valves that may lead to spintronics-based graphene devices; and nano-electro-mechanical devices.

Spintronics-based MOSFETs will also be reported, seen as one of the alternatives once CMOS technology has outlived its usefulness. Toshiba researchers integrated ferromagnetic tunnel barriers with silicon for the first time ever and will report on it at the IEDM. The researchers will discuss fabrication techniques and observations of spin transport.

Also very much in the “cool” category is work from UC-Berkeley. At IEDM, researchers will describe a wetting-based technique used to build self-aligned organic transistors and circuits with a minimum overlap of just 0.78µm. Everything was inkjetted — the semiconducting layers, metallization and dielectrics. The researchers say the process is simple enough that inexpensive all-printed circuits may be realized in the near future.

While it’s very easy to get excited about these and other promising advances that could potentially transform the semiconductor and related industries, a little reality check might be in order. For me, that came through an interview with Intel’s Mark Bohr, who described the company’s CPU and SoC technologies that will be presented at this year’s IEDM.

The company’s official description (provided in the tip-sheet) is this: Intel researchers will discuss a flexible, modular, mix-and-match 32-nm technology platform for advanced systems-on-a-chip (SOC) for diverse applications, including high-performance computing, low-power operation, and integrated RF/analog functions. The technology has a high-k/metal-gate architecture with three different transistor types (two with the same gate stack but different junction implants). It can support up to 11 interconnect layers, offers RF/analog passive elements, RF noise-mitigation features, and embedded memory with options for high-density (0.148µm2 cell size) or low-voltage (0.171µm). The technology demonstrated excellent reliability and enables ultra-low-power, high-performance and high-voltage-tolerant devices to be combined on the same silicon, in order to span a wide range of power, performance and feature requirements.

What’s interesting to me here is that Intel is not talking much about new process technologies, but rather the evolution of SoC. Intel first unveiled an SoC chip with the 45 nm (internally a “dot” version, the p1266.8.). With the 32 nm version and moving forward, Bohr said there are enough significant differences between the SoC and the CPU version to give its own number to the SoC version. 1268 is the CPU version, the 1269 is the SoC version of 32 nm.

Intel’s 32 nm, and most likely the 28 nm, transistors for both CPUs and SoCs use high-k metal gates (HKMG), strained silicon and employ immersion lithography. What’s interesting to me is what they do not employ: no tri-gate designs and no III-Vs in the channel region, for example. “Those types of more exotic solutions are not needed at this generation although we are continuing to explore them in our research group for future generations,” Bohr said. “Keep in mind though that high-k metal gate is still relatively new. Intel is the only company shipping high k metal gate and we did that successfully at 45 and this is the second generation so there’s still more to squeeze our of high k metal gate technology.”

Ditto for next-generation lithography solutions. “We think immersion lithography will be with us for a few more generations. We’d like to have EUV but it looks like it just won’t be ready in time for 22 nm and maybe not even for 15 nm. In the meantime, we’ll have to make do with immersion lithography and we think a greater use of double patterning techniques will be the way to do that – to extend immersion before EUV is ready. The nanoimprinting idea has been out there but I’m skeptical about whether it is going to be very viable for manufacturing applications,” Bohr said.

Instead of the exotic, Intel is instead emphasizing SoC products, which tend to require a broader range of device types. “In addition to the normal logic transistors, you need to include analog device elements such as inductors and precision capacitors. You also need to provide a wider range of transistor types from the high performance transistors used on CPUs to some very low leakage, low power transistors needed where long battery life is important. Also system on a chip products need to support a wider range of legacy I/O voltages, thus we have to add some special transistors that are tolerant to higher voltage conditions,” Bohr said.

SoC chip also have different interconnect requirements. “For the metal interconnect system for CPUs, those interconnects tend to be optimized for higher performance meaning some of the upper layers tend to use thicker and wider copper lines than the lower layers. That’s to provide higher speed interconnects across the surface of the chip. But for SoC products that run on lower frequencies, they don’t need the same higher performance interconnects. They may prefer a high density interconnect so we offer a different interconnect system for the SoC products providing fewer metal layers if low cost is important or more metal layers if increased interconnect density is important,” Bohr said. “Next we provide a range of advanced passive device elements such as precision resistors, capacitors and high-Q inductors, and a range of embedded memory from the very smallest, dense SRAM cells to low voltage SRAM to high speed SRAM. For our SoC product design, we offer this rich mix and match feature set. They can choose which features best meet the needs of their individual SoC products.”

In general, Intel plans to stay on its well established two year cadence, but moving to a dual platform approach, introducing both a CPU-specific and SoC-specific version of each technology. Production of 32 nm products is just starting this year: the end of 2011 should see 22 nm products, with 15 nm introduced at the end of 2013. How soon will we see some of the more exotic technologies such as graphene and spintronics in volume production? Not soon, given the conservative nature of the industry. Instead, it’s going to be all about integration.

Here’s what Mark Bohr told me, with a few slides to illustrate his points:

"We have two papers describing our 32 nm technology that were accepted for the IEDM. The first of those two papers describes in more detail the transistors used on our high performance CPUs for 32 nm. The second paper, Intel will be disclosing for the first time the technology that we’ve developed for 32 nm SoC products. Those two technologies are very similar, they share a lot of steps, but we’ve done some extra things, added features specifically for 32 nm SoC products. Both of these technologies use our second generation high k metal gate transistors which provide the highest drive current, the lowest leakage current and the tightest transistor gate pitches of any reported 32 nm or 28 nm technology.

The third key message is our 32 nm CPU process is certified. We have Westmere CPU wafers moving through the factory in support of a plan to keep with our revenue projection.

We reached a milestone on our 45 nm technology. We’ve shipped more than 200 million CPUs on that technology using high k plus metal gate transistors. That successful experience at 45 nm will help lead to a successful ramp of 32 nm products.

Regarding Intel’s naming system for the various logic technologies we’re developing or have in manufacturing: Not only are we continuing a 2 year cadence between technology generations but we’re now developing both CPU and SoC versions of each of these generations. The 45 nm generation, the CPU version is named p1266, the SoC is what we call the 1266.8. But now with the 32 nm generation, not only do we have these two versions but we’ve recognized that there are enough significant differences between the SoC and the CPU version to give its own number to the SoC version. 1268 is the CPU version, the 1269 is the SoC version of 32 nm. We’ll continue this going forward. At the 22 nm generation we’ll have both the P1270 and the 1271 for SoC products.

At 45 nm we were the first to introduce high k plus metal gate transistors, started shipping in volume in November of 2007 and so far we’re the only company shipping high k metal gate. It’s now down to very low defect levels and it is Intel’s highest yielding process ever. Even with the introduction of these revolutionary high k plus metal gate transistors, we have also achieved the highest yielding process ever.

Intel’s CPUs range from a single core up to eight cores. A back of the envelope calculation: 200 million CPUs adds up to more than 50 quadrillion transistors. That’s a five with 15 zeros after it. That’s enough for every 7 million transistors for every man, woman and child on our planet!

This is the second generation of high k metal gate transistor technology. We use 9 copper plus low k interconnect layers. This generation we’re introducing immersion lithography and that provides about a 0.79% scaling of the minimum pitches. This technology is also lead-free and halogen free packages.

The following graphic illustrates Intel’s trend in scaling the transistor gate pitch which is probably the most important design rule on a logic technology. It’s an indication of how closely you can pack transistors together. We’ve been scaling that design rule by about .7X every generation and now with the 32 nm generation, it’s been scaled down to a pitch of 112.5 nm. That is the tightest gate pitch of any reported 32 nm or 28 nm technology.

Some may have the impression that a 28 nm technology might be denser to what Intel has at 32, that’s not the case at least in the case of transistor gate pitch.

Intel’s trend for increasing transistor drive currents is certainly an important factor in performance. While we’ve been scaling gate pitch, we’ve also been able to continually increase drive current through the introduction of things like strained silicon technology at the 90 nm generation, then high k metal gates at 45. The driver currents on our 32 nm process are the highest reported drive currents for any reported 32 nm or 28 nm technology.

Here we illustrate Intel’s tick tock development model showing how every year we alternate between introducing a new micro architecture or introducing a new generation of process technology. Westmere is the name of the first product on our 32 nm technology. This is referred to as a tick product in the tick-tock scheme because it is the first product on our new process generation while retaining or extending the micro-architecture that was introduced on the 45 nm Nehalem product. If you recall, Intel did our first public demonstration of our Westmere CPU chips working in systems back in January of this year. Now we’re about to enter the fourth quarter and we’ve begun our production ramp for Westmere.

Defects have come down rapidly. Yields are now high. They are up to the level needed to begin a production ramp. The defect trend is offset by less than two years compared to our various successful 45 nm technology. Our process is certified and CPU wafers are now moving through the factory in support of planned Q4 revenue projections.

As we announced in February. Intel has four factories coming up on the 32 nm technology. D1D in Oregon is the first followed by D1C in Oregon, Fab32 in Arizona and Fab11X in New Mexico. Intel is investing about $7B in these factories to install the equipment and get them ready for manufacturing 32 nm products. D1D the equipment has been installed for some time now. We’ve already begun the production of the Westmere chips. D1C is just finishing the installation of that equipment. Fab32 and Fab 11X are in the process of installing equipment.

All for now.. stay tuned for my compelling Q&A!

The EUPVSEC (European photovoltaic solar energy conference and exhibition) was well attended, with 4000 registrants from 73 countries. More than 39% were from Germany and only 11% from the U.S. 943 exhibitors represented 34 countries, 49% from Germany, 10% from China and 9% from the U.S. By my rough estimate, about 1/3 of the exhibitors were pv cell/module suppliers, predominantly crystalline silicon, the rest thin film solar. The other 2/3ds were equipment and materials suppliers, along with quite a few BOS suppliers (inverters and the like).

It was like drinking from the proverbial fire hose in some ways, but whether through luck or my natural inclination, I wound up speaking with quite a few people involved in one particular aspect of the manufacturing business: the screen printing/drying/firing of conductive pastes. This blog will provide off-the-cuff take-aways from those conversations.

To digress just slightly, I can say that crystalline silicon is alive and well. There’s no question that much of the new capacity that has been recently added or is in the works is crystalline silicon (mostly mulitcrsytalline but some poly). Much of the focus of new equipment introductions is indeed aimed at that market – not so much in terms of advancing the technology (although there was some of that in terms as such “advanced” tech as more sophisticated process control) but more on increasing throughput and reducing breakage.

Throughput is frankly staggering compared to what’s found in semiconductor manufacturing. Typically numbers are 2400 wafers per hour, with capability to extend to more than 3000 wafers per hour. Almost all tools are belt-drive in-line tools (at least in screen printing/drying/firing). Increasing throughput is typically a matter of adding more modules to the in-line system: wafers need to see a certain amount of temperature over time so a longer furnace/firing section enables the wafers to be pushed through faster yet see the same amount of temperature (or the same amount of heat to be more precise).

Throughput can also be increased by putting two or three wafers across the belt instead of just one, as least in the drying/firing stage. The challenge in doing so is that the volatile organic compounds (VOCs) produced as the paste cures are fairly nasty to handle. They are can collect on chamber surfaces and then drop onto the wafer (if not properly removed) and I suppose pose some health hazards (if I was working with these machines on a daily basis I’d be VERY concerned about how these VOCs are captured and exhausted and potential exposure levels).

Now for a word about printing conductive pastes. Silver-based pastes go on the top of the wafer in thin grid lines and thicker bus bars. Aluminum-based pastes go on the back of the wafer in a blanket film (the whole thing forming a simple p-n junction).

Because it’s desirable to block as little light as possible from entering the cell, the top lines should be very thin. Yet, they need to carrying an acceptable amount of current for optimal efficiency. Because screen printers can only deposit films with a thickness of about 20-25 microns, a double print process has come into play, where the bottom line is printed and dried. The wafers are flipped and the backside contact is applied and dried. Again the wafers are flipped and a second front side line is applied directly on top of the first. It’s desirable for this line to be “high and tight” with straight vertical profiles to maximize conductivity.

An added complexity to this whole scenario is that there’s a push to make wafers thinner in order to minimize costs/achieve optimal out put of the wafering process (wafers are typically sawn with a wire saw from a brick into wafers – making them thinner means more wafers/brick). Wafers are now typically 190-200 microns thick. There’s a push to make then 140 microns or thinner. This, of course, increase the chance of the inevitable breakage. “Acceptable” breakage numbers I heard at the show range from 1 in 3000 to 1 in 5000 to 1 in 10000. The suppliers I talked to seemed confident about the ability to keep breakage under control, it being mostly a matter of how the wafers are handed off to and from a fast and slow belt respectively (machines may have three different belts moving at different speeds to optimize drying/firing conditions).

Work is underway to develop new conductive pastes that provides a better profile control when printed in thick layers. Sources say 5-6 suppliers are pursuing new technologies, some including nanocomposites to achieve the desired results. It’s not all that different from the conductive pastes used in surface mount technology, so perhaps my colleagues at SMT might have some insight here.

One final note: the heating technology used in drying and firing furnaces is typically either convection heating, infrared lamps or uv lamps. Surprisingly, there was little discussion about many of the things that are well known issues in the semiconductor such as the size of the grain, grain boundary interfaces, the structure of the grain, etc., all of which can have a significant impact on resistivity.

One postscript: IMEC was promoting the idea of electrochemical deposition of copper lines as an alternative to silver. Copper lines are cheaper and can easily be printed at finer dimensions. Also new: Applied Materials introduced the concept that it was possible to achieve higher efficiencies, but by going from 9 process steps to 14. No doubt this is true, but guess who would supply the five new steps?!?

More laterâ??¦ all I can say is I am fired up about PV (in my best Governator accent).

Here you will find easy access to five different PennWell brands that address Electronics and Electronics Manufacturing: Solid State Technology, Photovoltaics World, Small Times, Advanced Packaging and SMT. Each brand corresponds to one of our topic centers: semiconductors, photovoltaics, nanotech MEMS, and surface mount technology. Navigate through our topic and subtopic centers to find the latest news and tech features, or use the search function to access all of our content, including the archives. It’s all here!

The reasoning behind ElectroIQ is simple. Increasingly, similar process technologies are being applied across the various industries addressed by our five different brands. Screen printing of conductive pastes, for example, is used in printed circuit board assembly as well as photovoltaics manufacturing. 3D integration is an Advanced Packaging concept, but largely uses semiconductor front end process type steps. Chips are being embedded in printed circuit boards, nanotechnology is being implemented in semiconductor manufacturing and packaging materials. MEMS are integrated (and packaged) with energy harvesting devices and thin film batteries. The list goes on, up and down — and across– the entire supply chain.

We’ve worked hard to make sure that each brand continues to maintain its own identity, and that you know the source of everything you read. What we’re excited about is that with the increased functionality of the new site (made possible by a new software platform), we’ll be able to more easily identify and link to content that applies to our many different topic centers.

Coinciding with the new launch, we have restructured our editorial team. Debra Vogler, based in San Jose, will handle all technical feature content and submissions for SST, Advanced Packaging, Photovoltaics World and Small Times ([email protected]). Jim Montgomery ([email protected]) is responsible for news posting and wire news feed. Please direct press releases and news leads to him. New to the team is Steve Smith ([email protected]) who has taken on Managing Editor responsibilities.

Heading up SMT editorial efforts is Meredith Courtemanche ([email protected]). All editorial submissions and inquiries regarding SMT should be directed to her.

Welcome again. As always, please let me know what you think! You can reach me by e-mail at [email protected] or by phone at 603-891-9217.

Pete Singer
Editorial Director

I just started reading a new book titled "The Lean Manager, A Novel of Lean Transformation," and I’m already hooked. The authors, Michael and Freddy Balle, have taken what some would consider a pretty dry topic — the Toyota Production System — and brought it to life through a character by the name of Jenkinson, a new CEO at a fictional manufacturing plant.

A quick excerpt:

"Jenkinson stopped in front of a press, watching the robot hand slide in and out of the mold, picking up the finished part and dropping it on the conveyor, where an operator would deburr the part and place it in the customer packaging.

"Weekend shifts?"

"At the moment, we’ve had some press breakdowns so we need to catch up, and we’ve still got the parts that were supposed to be transferred to Romania. We’re running seven days a week on those."

"Come on!" the CEO had exclaimed irritably, with an outstretched hand encompassing the press area. "Look around you, a third of your presses are standing idle!"

Ward kept his expression carefully blank, and said nothing. What was there to say?"

I never thought I’d read a novel that casually incorporates EPITDA and injection molding, but so far, so good. Now, how to apply it to the publishing business?