Brian Krzanich, chief executive officer of Intel, said Intel is standing firm on 450mm development (despite rumors to the contrary), during a quarterly conference call with financial analysts. He also blamed defects on a slight push-out of next-generation 14nm technology.

When asked about 450mm plans, Krzanich said: “We have not changed our timing. We are still targeting the second, latter half of this decade. We continue to see great value in 450. It brings tremendous economic value to everybody who participates in it. We continue to work with our partners. We are here part of the joint development program in New York, continuing to work on 450. We continue to work with our partners, especially TSMC and Samsung and we are still targeting the back half of this decade. This is a long 10-year program when you really take a look at it. So I think you will get mixed signals throughout those 10 years,” he said.

As noted in my last post, progress is on track at the G450C consortia — an initiative by five big chip makers, Intel, TSMC, GLOBALFOUNDRIES, IBM and Samsung, partnered with New York state and CNSE — to develop 10nm capability on 450mm wafers in 2015 or 2016.

Krzanich also commented on the status of the firm’s 14nm roll out. “We continue to make progress with the industry’s first 14nm manufacturing process and our second generation 3D transistors. Broadwell, the first product on 14nm, is up and running as we demonstrated at Intel Developer Forum, last month. While we are comfortable with where we are at with yields, from a timing standpoint, we are about a quarter behind our projections. As a result, we are now planning to begin production in the first quarter of next year,” he said.  

When asked about why the delay, Krzanich said it was “simply a defect density issue,” and said it was just part of the development process. “As we develop these technologies, what you are doing? You are continually improving the defect densities,” he said. “As you insert a set of fixes in groups, you will put four or five, maybe sometimes six or seven fixes into a process and group it together, run it through and you will expect an improvement rate occasionally as you go through that,” he said. He said the fixes don’t deliver all of the improvements. “We had one of those,” he said. “Why do I have confidence? Because, we have got back now and added additional fixes, gotten back onto that curve, so we have confidence that the problem is fixed, because we have actually data and defects and so that gives us the confidence that we are to keep moving forward now.”

Intel has already started construction on a 450mm pilot line at its Ronler Acres location on Northwest Highway in Hillsboro. The D1X module 2 is about the same size (1.1 million square feet) as the original fab D1X and is built specifically for 450mm wafers. When the second module is complete, it will start up on 450mm wafers once it is equipped with appropriate manufacturing tools and gear.

Intel is currently equipping its D1X development fab to process 300mm wafers using 14nm manufacturing and expects to initiate production this year. While the D1X module 1 facility is 450mm-capable, it will come online as a 300mm fab.

Image by Portland Business Journal.

TSMC is the only other company with an effort underway to develop a 450mm production facility. In June 2012 it was reported that the Taiwanese government had approved a proposal to build a 450mm wafer fab in central Taiwan early in 2014. TSMC said back in 2011 that it planned to install 450mm pilot lines within a couple of established wafer fabs — Fab 12 in Hsinchu and Fab 15 in Taichung, Taiwan.

At Semicon Europa last week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

G450C is an initiative by five big chip makers — Intel, TSMC, GLOBALFOUNDRIES, IBM and Samsung – partnered with New York state and CNSE. The main goal is to develop 10nm capability on 450mm wafers in 2015 or 2016. “What we have to demonstrate is that a film on 300mm, when we scale it up to 450mm, we can do it with the same capability and, more importantly, at a very significantly reduced cost per process area. In other words $/cm2 need to go down significantly. That’s how you hit the scaling that we’ve typically seen in a wafer transition which is in the 30% range,” Farrar said.  

G450C aims to develop 10nm capability on 450mm wafers in 2015/2016.

Farrar said the facility looks quite different now than it did in March, when it was fairly empty. 18 tools have been installed so far, with a total of 25 tools delivered into the Albany complex by the end of 2013. “2013 is the year that I call install and debug,” Farrar said. “We’ll have approximately 50% of the toolset in the facility by the year end. It doesn’t mean that they’ll all be up and running but they will be placed in Albany or virtually at the suppliers, with about 35% of the toolset coming in 2014 and the last little bit that will be delivered will be the lithography tool in early 2015.” The program is organized around unit processes, including: film deposition and growth, wafer clean and strip, CMP and other processes, inspection and metrology, etch and plasma strip, and lithography.

In call cases, G450C will have at least one process that will be required for the 14nm flow. In most cases (about 70%) they will have multiple suppliers, at least two and sometimes three. “At the end, we’ll have both unit process and what I would call modules – 2 or three step processes – demonstrated. And then our member companies will take those building blocks and they will put their devices and their IP and then go build out factories,” Farrar said.

Farrar showed data demonstrating significant progress in wafer quality. He noted that they now have one wafer supplier and a second one coming on line. He also said automation and carriers were working well. “I don’t think they’ll be showstoppers. There are always things you can learn but those are working reasonably well,” he said.

G450C is also trying to take advantage of having a clean slate to make a switch from notched wafers – which provide a useful indicator regarding the crystal orientation of the silicon – to notchless wafers, which are perfect circles. “If you think about the physics around a notch, it really makes it difficult to get uniform films,” Farrar said. “A circle is a lower stress form. We get 1-1.5% better in getting closer to the edge. Using chips around the notch and perhaps getting to 1.5mm edge exclusion. We won’t get there if we don’t have notchless wafers. Our goal is to collaborate with our IC makers, our tool suppliers and materials suppliers, along with our facilities group.”

Probably the most critical part of the 450mm puzzle is lithography. Farrar said the consortia has been working with Nikon. “We were able to work with Nikon so that we now have immersion capability, in Japan, starting in June of 2014 and we’ll then have that tool installed in Albany at the end of the first quarter of 2015. We will have a true lithography capability which will enable us to get the efficient and actual process recipes that the deposition supplier will need to see so that they can demonstrate the capabilities at the 450 wafer form factor,” he said. “In the interim, we’re working on DSA (directed self assembly). We’re starting to see some pretty good results. I don’t think this will be a high volume technique but it’s a way that we can get something that works started in the early process modules in 2013 and early 2014.”

Wafer quality has improved, and wafer reclaim efforts are underway. “When we started this program, we had a handful of wafers. That was in the 2012 timeframe. We started to get reasonable test and monitor wafers in late 2012, and if you look at where we are today, in the 2^nd half of 2013, we have a quality spec where we’re hitting bout 98% of the area is in spec, and the particle level is effectively every wafer is meeting the specification. We still need a little work on wafer flatness,” Farrar said. The next step is what he called “prime” wafers, which they expect to have in the middle of 2014.  

The way in which logic and memory technology is likely to evolve over the next six years was provided at imec’s recent International Technology Forum in Leuven, Belgium. An Steegan, senior vice president process technology at imec, said that FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019). In DRAM, the MIM capacitor will give way to the SST-MRAM. In NAND flash, 3D SONOS is expected to dominate for several generations; the outlook for RRAM remains cloudy.

As shown in the Table, the 14nm node (which imec calls the “N” node”) is in development today, heading toward early production in 2013/2014. That will be followed by the N10 node in production at the end of 2015 and beginning of 2016. Then N7 and N5 will follow in 2017 and 2019.

Imec’s view on the future technology roadmap for logic and memory.

The most notable evolution in the logic roadmap is that of device architecture, where planar devices are being replaced by fully depleted devices. There are two main flavors of fully depleted devices: fully depleted SOI (FDSOI) and finFETs.  Imec sees FDSOI as an option for 14nm, which is “actually a speed push option from 20nm,” Steegen said. “What’s happening is that in the 14-16 generation, speed push knobs are implemented on the technology roadmaps to get the extra performance boost for that node.” That’s partly driven by the readiness (or really unreadiness) of EUV.  “Scaling is not necessarily the .7X one dimensional scaling that you expect node to node,” Steegen said. That’s why, in the 16-14nm generation, planar devices are being replaced by a higher performing fully depleted device. “When you push this to 10 and 7nm that we believe that the finFETs are going to have a long lasting life,” she added, which means that we will see finFETs on the roadmap for at least three generations.

The two main advantage of fully depleted SOI versus planar: 1) area footprint. You always get more performance from a trigate device since you actually use that third dimension. 2) Power/performance benefits.  

Steegen said imec is now mainly focused on assessing processes for 7nm and trying to figure out when the ultimate finFET scaling limit will be hit. At that point, expect to see what imec calls “local SOI,” which is a slight undercut of the bulk silicon fin to provide better isolation in the well. A more extreme version gate all-around device, which could be based on silicon nanowires.

To boost performance in the past, external source/drain stressors were used to increase electron and hole mobility in the device. The problem moving forward, in the N10 and N7 generations, is that there’s no space to do that. Instead, expect to see replacement of the silicon channel with a high mobility material.  “When you look at what material that could be, germanium is a good candidate to push hole mobility, so the PFET. And III-V, InGaAs, is a good material for NFET devices to push the electron hole mobility,” Steegen explained.

As far as standalone memory (vs embedded memory) goes, STTRAM is now being pushed forward to basically replace the MIMCAP on the DRAM roadmap. That’s because it’s very challenging to get an EOT of 0.3 (see table) and maintain acceptable leakage of the MIM capacitor.

For NAND flash, Steegen said the two-dimensional hybrid floating gate integration flow is definitely being pushed to a 15 and 13nm half pitch. “Scaling is one challenge you’re going to encounter here. The other one is the charge you can trap on the floating gate itself. It becomes so discrete there’s hardly any charge left. The variability you’re going to have on the hybrid floating gate concept is likely getting too big. That is why 3D SONOS is definitely getting it’s way in on the NAND flash replacement roadmap and also we forecast that to have quite a long lifetime: two or three generations,” she said.  

Steegen said the outlook for RRAM was cloudy. It could be the eventual successor to 3D SONOS, but “if you want to replace 3D SONOS, you’re getting to need 3D RRAM because you’re going to use the same 3D configuration. Also, for NAND flash replacement, you always need that select element to make sure you only select that one cell you want to turn on. How to integrate the selector with the RRAM element in a 3D configuration is going to be the trick of how RRAM can enter this NAND flash roadmap at the end,” she said.

At the recent imec International Technology Forum Press Gathering in Leuven, Belgium, imec CEO Luc Van den hove provided an update on blood cell sorting technology that combines semiconductor technology with microfluidics, imaging and high speed data processing to detect tumorous cancer cells.

As I reported previously, the challenge is huge: one has to have the ability to detect one bad tumor cell in 5 billion blood cells. This equate to a requirement to detect 20 million cells per second.

“We all know that cancer is one of the most severe illnesses, creating a tremendous burden on the patients, on families and on society,” Van den hove said. Cancer spreads throughout our body through circulating tumor cells that originate from the primary tumors, and create secondary tumors. Usually those are the most fatal ones. “If we can develop a system that can detect those circulating tumor cells in a very early phase, we develop an early warning system for cancer,” he added.

Today, single cell analysis requires a lot of manual operations, sophisticated (and expensive) tools that require a lot of time to generate the results. Very often those results are not accurate enough or not sensitive enough. “What we actually need is a much more engineering type approach where we start from the clinical samples directly, and one that is much more automated. At imec, we are developing a high content, high throughput cell sorter, which is much more compact than any cell sorter ever made. We have demonstrated the proof of principle of operation of such a cell sorter,” Van den hove said.

Here’s how it works: When a blood sample is loaded into the system, the cells flow in via the main microfluidic channel. The sample contains a whole range of cells. Several types of white blood cells, red blood cells, platelets, and even maybe some rare blood cells, such as circulating tumor cells. The microfluidic channel is about 30 microns wide, about the size of a single cell. Conditioned light illuminates the cells and results in fringe patterns that are recorded by the CMOS image sensor. These fringe patterns contain information on the 3D structure of the cell. The recorded holograms are then reconstructed into 2D images that are used to distinguish between the different types of cells based on cell size and nuclear morphology. These calculations, managed by an ASIC, need to be performed very quickly before the cells arrive at the microheaters further down the channel. The microheaters located at the crossings of outlets, generate small and short-lived steam bubbles that gently but quickly push single cells to a particular outlet. While the red bloods cells just go straight on, the while blood cells are brought to the lower outlet and the tumor cells are pushed in the upper outlet. The sorted cells can then be further analyzed downstream. For instance, by extracting specific molecular information. After sorting, high resolution 2D or even 3D imaging of each single cell can be consulted for further visual analysis.

Imec has so far demonstrated all the building blocks of this technology and demonstrated proof of principle with a single channel. The next step is to build thousands of channels on a single chip. “With silicon technology, we can very easily integrate thousands of those channels on one chip and in this way, realize the enormous sensitivity that is needed in order to detect these bad tumor cells in a billion cells. The system we’re developing will be able to process more than 20 million images a second. This kind of tool will bring one to bring this kind of analysis from a very sophisticated lab to the side of our bed and provide much better accuracy,” Van den hove said.

Despite some economic woes in recent years, Europe remains dedicated to building a strong electronics industry. This was brought home to me recently when, in advance of Semicon Europa (October 7-10 in Dresden), I had a chance to talk with Heinz Kundert, president of SEMI Europe. “There are several initiatives like the KET (key enabling technology) initiative that are working on the same goals to increase the competitiveness but also to get more manufacturing back to Europe,” he said. One of these is the Horizon 2020 effort, the EU’s new program for research and innovation is part of the drive to create new growth and jobs in Europe, which will run from 2014 to 2020 with a budget of just over €70 billion (some announcement during Europa is planned). France also announced Nano 2017 and plans to invest approximately €3.5 billion in France up to 2017 in nanoelectronics.

Another interesting project, specifically aimed at boosting semiconductor manufacturing in Europe is the 10/100/20 program, which has a goal of generating €10 Billion in public/private funding for R&D, €100 billion euros investment for manufacturing, and 20% share of global chip production market by 2020. Neelie Kroes, European Commission Vice-President, commented in May of this year: “I want to double our chip production to around 20% of global production. It’s a realistic goal if we channel our investments properly. A rapid and strong coordination of public investment at EU, Member State and regional level is needed to ensure that transformation.”

Already, some significant progress has been made. Five new pilot lines were launched in May 2013 under the ENIAC Joint Undertaking (EU public-private funding program), worth over €700 million and bringing together over 120 partners. These pilot lines allow research centers and companies to cooperate across borders to test and perfect new technologies and tools, such as: technologies and equipment for GaN-based substrates; 450mm equipment and materials; 300 mm power semiconductors; new MEMS materials and packaging; and 28/20nm FD SOI.

In the past, Europe was home to around 17% of global semiconductor manufacturing, but that has declined to around 6-7% today. Turning that around to reach 20% in the next seven years will be a challenge, but where there’s a will there’s a way. “Although there are a lot of issues, and a lot of details that need to be clarified – many people are questioning whether it’s possible or not possible — but what I see is positive thinking and this is most important,” Kundert said.

If you plan to visit Semicon Europa and want to learn more, you’re in luck. “We will address all these issues on public funding, public/private partnership vision at Semicon,” Kundert said. There will be an executive summit this is addressing that issue, as well as sessions on funding to explain how SMEs (equipment suppliers) can participate. “Projects are going to be presented so people understand what’s behind all these initiatives and visions and big numbers,” he added.

Please join us for a free webcast on Advanced Packaging, to be held on September 30^th, at 11:00am Eastern, 10:00am Central and 8:00am Pacific. You can register in advance at this link: https://event.webcasts.com/starthere.jsp?ei=1021830

The webcast, which will feature presenters from Texas Instruments and Micron, will address how today’s packaging technology is driven by a combination of cost, performance, form factor and reliability. The presenters will examine new advances in conventional back-end packaging, including wafer bumping and copper wire bonding, as well as the role of new 2.5D and 3D integration. They will also focus on issues related to cost, performance (speed, power and noise immunity), form factor (thickness, weight, PCB area consumption), and testability, as well as the tradeoff of technical maturity versus risk in high-volume manufacturing. The webcast will also include new information on the Hybrid Memory Cube, a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections. This is a revolution in 3D integration packaging technology, as covered in our September issue cover story.

Our first speaker, will be Dr. Mahadevan “Devan” Iyer. As Director of TI’s Worldwide Semiconductor Packaging operations, Dr. Iyer oversees a global team that drives a process to determine the packaging design and technologies that best meet the requirements of our customers in measures of miniaturization, performance cycle time, and cost. Dr. Iyer joined TI in 2008 to lead the global SC Packaging team. He has more than 25 years of experience in the microelectronics industry. Dr. Iyer is a recognized authority in semiconductor packaging technologies.  He has more than 150 technical publications and 28 patents to his credit.

Our second speaker will be Aron Lunde, a Product Program Manager for Micron’s Hybrid Memory Cube.  His responsibilities include coordinating Micron’s internal departments to develop, construct, and deliver the HMC to meet the demands of multiple business engagements. Mr. Lunde joined Micron in 1994 and worked as a Test Engineer for Micron’s Boise, Lehi and Singapore facilities.  He later worked as a Mobile DRAM Designer, implementing repair and test modes on original Micron designs, integrating repair schemes into DRAM and mobile device architectures, and developing tools to evaluate the efficiency of repair schemes. Mr. Lunde has a BS in Electrical Engineering from the University of Idaho and has issued 15 patents.

Thanks to our webcast provider, TalkPoint, you’ll be able to tune in using any mobile device including iPads, tablets and phones!

The webcast will be archived after the event and can be accessed for 12 months. Register now at https://event.webcasts.com/starthere.jsp?ei=1021830