Rick Wallace, president and CEO of KLA-Tencor, provided the keynote talk at the SEMI Industry Strategy Symposium (ISS) this year, held Jan 12-15 in Half Moon Bay, CA. He said he believes the semiconductor industry might be facing a “Concorde” moment, referring to the demise of supersonic passenger transport, the last flight of which was on 24 October 2003. “That failed not because of technology but because of economics,” Wallace said. He sees a similar challenge coming down the road for continued scaling. “Moore’s Law is much more likely to die in the boardroom than the laboratory,” said.

Wallace also spoke about “The Road Less Traveled,” seeming to indicate that the more traveled one is that of consolidation, which Wallace said leads to “losses in agility, flexibility and innovation.” He said larger firms are not effective at driving innovation although they are effective at driving continuous improvement. “It’s tough to see how a large scale merger makes a company better,” he said. “Some firms will be too big to fail but my fear is that they will become too big to innovate.”

The solution he said is young people. “We need to attract the young talent if we want real innovation. The longer you’re around the more you see what can’t be done,” he said.

Wallace told a story about explaining to his 10 year old daughter what his company by using the iPad as an example. His daughter thought about it and said she understood: it was the magic behind the gadget.

Part of attracting young people to the semiconductor industry is through education. After Rick’s presentation, Denny McGuirk, president of SEMI, presented an award to Rick and to L.T. Guttadauro, president of the Fab Owners Association, in recognition of their work on SEMI’s High Tech University (HTU). HTU is a career exploration program that encourages student interest in science, technology, engineering and match. Since 2001, the SEMI Foundation has delivered 143 programs to 4800 students and teachers worldwide.

Although some view the semiconductors as a commodity, hopefully efforts such as that of the HTU will explain the magic behind the gadget. “Who doesn’t want to work on magic?” Wallace asked.

The origin of Solid State Technology began in 1958, the same year that Jack Kilby of Texas Instruments invented the integrated circuit (the invention of the transistor is credited to Bell Labs; the first transistor was demonstrated on December 23, 1947). The initial name of the magazine was “Semiconductor Products” and that was changed to “Semiconductor Products and Solid State Technology” by 1962.  

In this news series, we’ll look back 50 years and see how much has changed.. or perhaps more often, how much hasn’t.  

In January of 1964, it was clear that microelectronics were here to stay, and were rapidly changing the shape of the electronics industry (Gordon Moore did not propose his now famous Moore’s Law until April of 1965, more than a year later. Intel was not founded until 1968). In the Editorial in the January 1964 issue, Editor Sam Marshall writes that estimates for the market for microelectronics in 1964 “vary between 25 and 50 million dollars.” The market exceeded $300 billion in 2013.

Sams adds: “There is a parallelism between the manner in which semiconductor devices have gradually displaced vacuum tubes, and the manner in which microelectronics is encroaching into the territory formerly enjoyed by discrete devices such as diodes and transistors. This movement is directly related to the increasing demands for higher frequencies of operation, greater miniaturization and surprisingly enough, reliability.”

Sam also foresaw how the relationship between design and manufacturing was getting more complex and even hints at the trends toward the fabless/foundry model. He said that a new order of procedure must be followed.  “The engineer must either turn over his proprietary design to a firm engaged in microelectronics manufacturing or he might search the open market for functional blocks that will best meet his needs. In either case, an unhealthy situation arises. In the first case, the design engineer has to reveal information which could jeopardize his firm’s market advantage. In the second case, the manufacturer who merely purchases functional blocks and assembles them into a product justifiably feels that he has lost his status as that of a true manufacturer and has become nothing more than an assembler and tester.”

The issue had a feature on electron beam processing of semiconductor devices, which noted how useful the analysis of X-rays generated from e-beams could be for metrology. “The technique is extremely useful in determining which elements are present on the specimen surface as well as detecting local variations in their concentrations after such treatments as localized melting, annealing, diffusion and oxidation.” Today, energy dispersive x-ray spectroscopy or (commonly called EDS, EDX or EDAX) is widely used.

Perhaps the most obvious change in the last 50 years: wafer size. Note these two advertisements, one touting a production breakthrough of 40mm wafers (that’s a little over 1.5 inches), the other depicting a wafering machine. Of course, today the industry is working with 300mm wafers and contemplating going to 450mm. It’s also interesting to note the die size, number of die per wafer and pincount shown on the left, although it’s hard to say if that was typical of the time.

Other odds and ends from 1964: Kulicke and Soffa reported its sales fro the fiscal year ending Sept 30, 1063, were $3,615,519, an increase of 95%. ITT planned to construct a 135,00 square foot, $3 million plant in West Palm Beach, FL to manufacture integrated circuits and other semiconductor devices. Philco Corp.’s Lansdale Division (which produced Indium Antimonide IR detectors among other types of electronics), planned to triple the divisions facilities for microelectronic engineering and product development, with plans to develop new production facilities capable of producing 10,000 silicon microcircuits per month by Spring of 1964. Total 1964 R&D expenditures in the U.S. were expected to reach the $20 billion mark. In 1963, about $18.3 billion has been spent on R&D compared to $16.6 billion in 1962. Advanced achieved with graphite and carbon as engineering materials were detailed by Speer Carbon Co.  A novel approach to the fabrication of a high speed tunnel diode was described by IBM: a gallium arsenide, planar, epitaxial device. Today, the potential of tunnel transistors is being discussed as a replacement to FETs. Based in part on what? Gallium Arsenide! The more things change…

Coming next month: GaAs IR emitters, tunnel diode amplifers and thermal resistance of transistors.

Hopefully everyone is familiar with the International Technology Roadmap for Semiconductors (ITRS). It was launched in 1992, when the Semiconductor Industry Association (SIA) coordinated the first efforts of producing what was originally The National Technology Roadmap for Semiconductors (NTRS). This roadmap of requirements and possible solutions was generated three times in 1992, 1994, and 1997. The NTRS provided a 15-year outlook on the major trends of the semiconductor industry. As such, it was a good reference document for semiconductor manufacturers, suppliers of equipment, materials, and software and provided clear targets for researchers in the outer years.

When the semiconductor industry became increasingly global, the realization that a Roadmap would provide guidance for the whole industry and would benefit from inputs from all regions of the world led to the creation of the International Technology Roadmap for Semiconductors (ITRS).

The invitation to cooperate on the ITRS was extended by the SIA at the World Semiconductor Council in April of 1998 to Europe (represented by the European Electronics Component Manufacturers Association [EECA]), Korea (Korea Semiconductor Industry Association [KSIA]), Japan (formerly the Electronic Industry Association of Japan [EIAJ] and now the Japan Electronics and Information Technology Industries Association [JEITA]), and Taiwan (Taiwan Semiconductor Industry Association [TSIA]).

Much has been written about the ITRS, which is perhaps the best roadmapping effort of all time in any industry. In fact, I stumbled across a dissertation titled “Technological Innovation in the Semiconductor Industry: A Case Study of the International Technology Roadmap for Semiconductors (ITRS)” written by Robert R. Schaller in his pursuit of a degree in philosophy at George Mason University. Robert did a great job analyzing the importance of the roadmap and includes anecdotes such as a short-lived attempt at AMD to create an internal roadmap, and how the ITRS relates to the roadmap to peace in the Middle East.

While the latest updates and revisions of the ITRS usually come out around this time of year, the organizers tell me that it will be in the spring of 2014 for the latest edition (which will be a full revision vs an update, which alternate every year).

A key aspect of the ITRS is that they go out of the way to NOT try to pick “winners and losers” as I’ve heard it called. It is clearly stated that: “The ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment”.

That’s all well and good I suppose, and there is plenty of information that a savvy supplier can pull from the Roadmap about what technology is needed and what the market demand might look like. But it’s time to take it to the next step.

It’s time to think about creating a roadmap for equipment and materials companies, and their suppliers (i.e., suppliers of critical components and subsystems and raw materials). I recently had a conversation on exactly this topic with Gopal Rao, SEMATECH’s senior director of business development. Prior to joining SEMATECH, Rao served as director of Manufacturing Research at Intel, where he led a strategic portfolio of advanced manufacturing projects in partnership with universities and national labs. A 24-year veteran of Intel, Rao progressed through a variety of assignments in senior engineering and management roles.

Gopal attended The ConFab 2013 as a representative of Intel, and said he found the private meeting with suppliers quite useful. What he proposes we do in 2014 was at least introduced the concept of a roadmap for equipment and materials suppliers, perhaps in a panel session, and suggest it be a common thread in the private meetings between sponsors (suppliers) and VIPs (delegates from IC manufacturing companies). We had more than 170 such meetings in 2013. At the end of the conference, we’ll come up with a list of 4 or 5 “action items” for the industry to address. I like this concept a lot, and it’s perfect timing since we’re just now defining session topics and recruiting speakers and panelists.

I like this idea a lot and will plan on adding it to the agenda. If we can define what suppliers need to deliver in terms of throughput, uptime, automation, footprint, uniformity (wafer-to-wafer and tool-to-tool), data reporting and communication protocol, in-situ inspection… and what else?

The ConFab 2014, by the way, will be held June 22-25 at The Encore at The Wynn in Las Vegas. Don’t miss it!

The International Electron Devices Meeting (IEDM) was held in Washington, D.C. this week. I attended a short course on Sunday focused on the Challenges of 10nm and 7nm CMOS Technologies, organized by Aaron Thean of imec. The speakers were Frederic Boeuf of ST Microlelectronics, who gave a general overview of drivers and challenges; Zsolt Tokei of imec, who spoke on interconnect challenges; Andy Wei of GLOBALFOUNDRIES who talked about process integration challenges, Paul Franzon of North Carolina State University who gave an overview of 2.5D and 3D stacked ICs, and Mark Neisser of Sematech of spoke on lithography challenges and EUV readiness for 10nm and beyond.

Monday morning brought three plenary speakers in the form of a talk on graphene integrated circuits by Andrea Ferrari from the University of Cambridge, a fascinating “super chip” concept presented by Mitsumasa Koyanagi from Tohoku University, and a most excellent talk by Geoffrey Yeap of Qualcomm Technologies on how smart mobile SoCs are now driving the semiconductor industry. During lunch, IEDM chairs Ken Rim of Qualcomm and Suman Datta of Penn State highlighted 15 of the top papers, many of them showing recording breaking results

I also attended an interesting evening panel session hosted by Leti that gave an overview of their electronics research efforts, a panel session hosted by Applied Materials on 3D NAND, and a luncheon talk by Eric Enderton of NVDIA research.

I’ll be summarizing what I learned in the coming weeks and months, but it was very clear to me that process technology (including litho) and process integration remains the most critical factor in determining success moving forward. In FinFET production, for example, a gate-last/high-k last process is detrimental to total parasitic capacitance compared to a gate last/high-k first approach. Hopes remain high for EUV – the urgent need for it was clearer than ever – but Andy Wei said it was not going to happen for 10nm (let’s leave it at that he said) and Neisser said the delay has already cause most companies to look earnestly for alternatives. He said DSA was showing great promise, particularly for vias, but it was difficult to assess progress since those involved were not yet publicly discussing results.

“A dream for the device engineer could be a nightmare for a process integration engineer,” said Boeuf in the opening talk. That seemed to be echoed throughout the conference, where the potential of new devices such as tunnel FETs or materials such as graphene were always tempered with a dose of reality that materials had to be deposited, patterned, annealed to create devices, and those devices had to be connected. There was also the perhaps inevitable discussion about how long the industry could continue scaling. We are “running out of numbers,” Wei said in a response to a question regarding what was after 7nm. “We’re running out of atoms,” he added. What was most startling was a comment from Serge Tedesco of Leti who said that ML2 and DSA, as cost effectives and complementary solutions, could extend 193i lithography to the end of the roadmap! The end of the roadmap? I have not given much thought to an end to the roadmap, although the ITRS looks out to 2026. For now, I’ll assume that means the end of conventional scaling, but I have to say I never want to see it end.  

We had our second conference call yesterday with advisory board of The ConFab (a special thanks to Lori Nye of Brewer Science who called in from Japan at 2:00 am her time. Above and Beyond the call of dutry!). The ConFab will be held June 22-25 at The Encore at The Wynn in fabulous Las Vegas, Nevada. It will be the 10^th anniversary of the event and I’m working hard to make it the best one ever.

We’ve recently updated the event website, www.theconfab.com. It includes a short video where, using my best radio voice, we scroll through pictures of last year’s event, including a not so flattering picture of Bill Ross of ISMI (sorry Bill!).

As you know, I travel around a lot, attending various semiconductor meetings and conferences. In fact, I’m off to IEDM tomorrow! Short courses begin at 9:00 am on Sunday and I can’t wait. It’s like drinking the Kool-Aid from a fire hose! But I digress.

The ConFab is vastly different from any other event I’ve attended for several reasons. For one, it’s focused entirely on the economics of semiconductor manufacturing. All of the keynotes and presentations are tuned to that direction. Yes, we get into technology challenges in design, manufacturing, packaging and test, but with a huge helping of why and at what cost? We may kind of sip the Kool-Aid but then talk about how it tastes (okay, any analogy breaks down at some point, but you know what I mean).

Another reason The ConFab is different: We combine thought-provoking conference sessions with private meetings arranged between our sponsors and our VIP attendees or “delegates” as we like to call them. These aren’t “speed dating” kinds of meeting, but 45 minute meetings where both parties come prepared to talk business. I’ve found this is one of the least understood aspect of The ConFab. People often ask me: “Why would leading semiconductor manufacturers feel the need to travel and sit down with their suppliers when they could just pick up the phone and call them whenever they want.” The answer to that is simple. One, it’s true they can do that, but those kinds of conversations are usually focused on some kind of problem. The tool isn’t working; get it fixed. We need this or that. I’m not privy to the private conversations in these meetings at The ConFab, but people have told me they’ve accomplished more in one day than would have in a year otherwise. They’ve also told me it was the first time they met with a customer and didn’t get yelled at.. but that’s a different story. I think it’s also true that most of the technology in a fab come from the tool and equipment suppliers (and software suppliers – let’s not forget EDA!). At The ConFab, they can at least touch base with all of their main suppliers and have useful meetings. People come to this absolutely fabulous hotel, which is easy to get to, relax and listen to luminaries discuss industry trends and challenges, and then sit down with folks that can make business happen. We combine all this seriousness with a variety of networking events, including breakfasts, lunches and evening receptions, as well as refreshment breaks.

At the 2013 ConFab, more than 175 private meetings took place during which sponsors and their customers, both prospective and existing, engaged in strategic discussions and created crucial alliances for the future. These pre-scheduled boardroom meetings offer an efficient and highly effective approach to conducting face-to-face business in a global industry

I was talking to Bill Tobey yesterday after our conference call. Bill, who is a true industry veteran, has been involved with The ConFab from the very beginning and has seen many things come and go. He reminded me that in the mid 2014 we will know a lot more than we do today. EUV alone – whether it works or not — is going to be a major factor in determining the “economic balance” as Bill put it. He said we should keep that in mind as we develop our session topics and invite our speakers. Sage advice if I’ve ever heard it. Bill was one of the co-founders of Micronix, which was focused on providing a single point X-ray solution. That didn’t take off because of problems with the X-rays masks. Guess what – the same problem still exists with EUV masks. But I digress yet again.

With Bill’s help – and the rest of our fantastic board members — we’re putting together the agenda for 2014. I’m more than confident that it will be as exciting as past years, when we had such speakers as: Y.W. Lee of Samsung, Subu Iyer of IBM, John Chen of Nvidia, Bob Bruck and Jackie Sturm of Intel, BJ Woo of TSMC, Ali Sebt of Renesas and many others (check out our most excellent lineup from this year).

We will be covering the economic outlook for 2014 and beyond, major technology challenges facing the industry – such as the move to 450mm wafers – and of course the big issues such as the escalating costs of R&D.

More on this later, but we are also planning a second ConFab event, The ConFab II, in November. This will focus on critical subsystems and components: all the things that go into today’s extremely complex processing and assembly tools, including robotics, vacuum pumps, pressure gauges, power supplies, exhaust treatment, wafer aligners, etc.

This is all a long-winded way of saying I hope you join us next June at The ConFab for our 10^th anniversary, and The ConFab II in November. Check out our website for more: www.theconfab.com.

Pete

P.S. If you’re interested in a sponsorship, contact Sabrina Straub at [email protected].

As part of the technical program at the annual IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013 at the Washington Hilton Hotel, a special focus session has been planned to highlight advanced processing and platforms for semiconductor manufacturing technology, including ‘more-than-Moore’ applications.

The technical session, scheduled for Tuesday, December 10 from 9am – 12pm, will feature presentations on many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Memory industry transition from planar to 3D scaling and the introduction of emerging memory devices into manufacturing over the next decade will drive several unique challenges. The inflection point faced by the semiconductor memory industry is a new paradigm where advancements in materials science, equipment technology, and control methodologies are critical for scaling cadence. This will be the focus of “Challenges in 3D Memory Manufacturing and Process Integration,” an invited paper given by N. Chandrasekaran, Micron Technology

The output power at high temperature required for LEDs applied in solid-state lighting can be obtained by reducing threading dislocation density (TDD) on silicon substrates using a new technology, SiN multiple-modulation interlayers, to realize highly efficient blue LEDs grown on high-crystalline-quality GaN templates on 8-inch silicon wafers. This will be presented in “LED Manufacturing Issues Concerning Gallium Nitride-on-Silicon (GaN-on-Si) Technology and Wafer Scale up Challenges,” an invited paper given by S. Nunoue, et.al., Toshiba Corporation

Recently, silicon photonics has generated a renewed interest in integrated optical communications.  A paper titled “A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications,” presented by F. Boeuf, et. al., STMicroelectronics will describe the main process features and device results for a 300mm silicon photonics platform designed for 25Gb/s and above applications, at the three typical communication wavelengths that are compatible with 3D integration.

A paper from TSMC will present the details of the first fabrication of a 300mm, 50μm ultra-thin glass interposer – a promising technology for future high frequency mobile RF applications.  The merits of on-glass inductors and transmission lines are compared to their on-silicon counterparts in Q-factor, power dissipation, and power/signal integrity. “300mm Size Ultra-Thin Glass Interposer Technology and High-Q Embedded Helical Inductor for Mobile Applications,” will be presented by W.-C. Lai, et. al., TSMC.

The first rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable 14nm SOI FINFETs, will be presented by A. Paul of GLOBALFOUNDRIES. The study identifies, threshold voltage (Vtlin), external resistance (Rext), and channel transconductance (gm) as three independent sources of variation. The variability in gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit (indicating local variations), along with non-zero intercept (which suggests global variations at the wafer level). Both n- and p-FINFETs show the above-mentioned trends. The paper is titled “Comprehensive Study of Effective Current Variability and MOSFET Parameter Correlations in 14nm Multi-Fin SOI FINFETs.”

The 450mm transition represents an opportunity to reduce die cost and stimulate another wave of innovations and greener manufacturing. Key challenges ahead, including tool productivity, uniformity, precision, cost-of-ownership reduction, and green concept design-in tool and manufacturing systems, are presented. “Opportunities and Challenges of the 450mm Transition,” is an invited presentation by J. Lin and P. Lin, TSMC.

In a keynote talk at The ConFab earlier this year, Samsung exec Yoon Woo (Y.W.) Lee. predicted that optical interconnects would soon be required. “Exascale computing will require optical interconnection to communicate between the CPU and memory chip,” he said. This appears to be moving closer to reality with last week’s demonstration by Fujitsu and Intel of the world’s first Optical PCIe Express (OPCIe) based server. 

Intel’s 50Gbps silicon photonics link was demonstrated in 2010, and it has now been put into practice. Just last week, Fujitsu said it has demonstrated the world’s first Intel Optical PCIe Express (OPCIe) based server.  In a blog, Intel’s Victor Krutul said that Fujitsu took two standard Primergy RX200 servers and added an Intel Silicon Photonics module into each along with an Intel designed FPGA.  The FPGA did the necessary signal conditioning to make PCI Express “optical friendly”.  Using Intel Silicon Photonics they were able to send PCI Express protocol optically through an MXC connector to an expansion box.  In this expansion box was several solid state disks (SSD) and Xeon Phi co-processors.

It’s commonly known that silicon is not a good material for generating or detecting light (although silicon dioxide is quite good at channeling light). Optical interconnects will require III-V lasers to convert electrical signals into pulses of light and, on the receiving end, photodetectors, typically germanium-based, to convert that light back into electrical signals. Intel has demonstrated that it’s feasible to directly integrate photonics with silicon CMOS in an impressive prototype, but most solutions will require some type of some type of advanced packaging, such as flip-chipped lasers.

During a discussion with Ludo Deferm, executive vice president at imec on interconnects – imec had recently released details about the benefits of manganese as a diffusion barrier and some work on low-temperature low-k etch – I asked him about optical interconnects.

For intrachip applications – such as between microprocessor and memory — Deferm said that will depend on the data rates required. “If you have 1000, 5000 parts to be connected over a distance of a couple of millimeters and you want to transfer a Gb of data, just copper lines can have some limitations,” he said.  “If you have the space — and it takes space — you can do it. But you will do that where you need the high transmission rates. There is no need to change the intrachip interconnects with photonics. But the interchip, between the different chips, we are working on that because we are even now providing photonics technology to startup companies and other companies who want to design in it.“

Part of the challenge is that various optical components are required – waveguides, detectors, modulators and polarizers, for example – and those are not available at standard foundries. Imec has a design kit and a library and IME in Singapore has capabilities as well.  

Deferm said these components are not so easily integrated. “Most of the problems are related to losses. Optical kinds of interconnects have the advantage – they’re good at data speed – but you have to be careful because you can create losses because you need wide ideal structures. Not because they have to be so small in dimension, but they have to be controlled very well over the edges: it is light and light scatters. You also have losses because of coupling,” he said. On a silicon substrate, a high frequency signal in Gb/seconds also creates coupling towards the substrate and that creates losses as well.

The new Solid State Technology Editorial calendar for 2014 – the whole media planner actually – is out and live on our site: http://electroiq.com/advertise-docs/2014mediakit.pdf

The editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics. In 2014, we’ll be looking at CMOS imagers, thin film batteries, OLEDs, smart sensors, and plastic electronics, among others.

We also delve into the process technologies – lithography, etch, deposition, implant, planarization – and materials. We will also be addressing over-arching topics such as metrology, contamination control, defect detection, thermal management, automation and supply chain issues. And, of course, the 450mm transition.

We’ll be covering these in the magazine (8X in 2014), on the website (www.solid-state.com and www.semimd.com), and through regular webcasts, newsletters, video reports and at our live event, The ConFab in June (www.theconfab.com).

If you’re interested in contributing material on these or other topics, just shoot me a line at [email protected], or give me a call at 978-470-1806 I look forward to hearing from you!

It’s well known that EUV adoption is running later than hoped, mostly due to inadequate source power (although ASML and Cymer say they are on track to provide workable solutions and imec says it’s on track for the 10nm node). After that, the main challenge could be those associated with EUV mask blanks, which are essentially sophisticated mirrors. The dual challenge there is that they are not only difficult to produce without defects, but they are difficult to inspect. Presently, the only way to really test them is to fabricate them and see what kind of pattern results after they’re used.

But another challenge recently came to my attention: the optics in the EUV system, which are also sophisticated mirrors made of multi-layer structure, get contaminated during operation. This degrades their quality over time, and eventually the system must be disassembled and the optics recoated or replaced.

I recently talked to Dr. Harro Hagedorn, head of R&D at Leybold Optics in Alzenau, Germany. Located about 20 minutes outside of Frankfurt, the company supplies evaporation and magnetron sputtering systems used to fabricate the multi-layer coatings used for EUV collector optics and or many other applications such as synchrotron labs and X-ray devices. And they work with ASML and Zeiss, and the Fraunhofer Institute.

Speaking on EUV, Dr. Hagedron, said the output of the light source is still not high enough, and also the lifetime of the optics was a concern. “This light source is normally an awful thing for the optics because you have a metal droplet that is heated up by a laser and then it creates a plasma. These metal droplets are also contaminating the optics,” he said. To correct, this “they have to disassemble the system and recoat these optics. They are very expensive. Also, the life throughput that comes from this light source and through the optics goes down. They have to also manage this,” he said.

Part of the complexity and expense of the optics is that they rely on interference coatings that require stacks of layers. “The challenge is that these layer stacks are incredibly thin, 3-4nm, with coating uniformities in the range of 0.1%,” Hagedron said. “It’s not any more than a diameter of an atom.” The goal for these optics is a reflectivity of nearly 70%.

Investigating a bit further, I found that there has been a significant amount of research into the lifetime of EUV optics. In fact, earlier this year in April, a session at SPIE was dedicated to damage to VUV, EUV, and X-ray Optics. One of the papers by Laser-Lab in Germany, KLA-Tencor and Fraunhofer, described work that characterized EUV damage thresholds and imaging performance of Mo/Si multilayer mirrors. Here’s a summary:

Currently, more and more powerful EUV sources for next generation semiconductor microlithography are being developed, for which novel optical elements like multilayer or grazing-incidence mirrors are required. Consisting of very thin alternating layers, especially molybdenum and silicon for the wavelength of 13.5 nm, multilayer mirrors are typically employed for near-normal reflection angles. These mirrors are presently being optimized with respect to thermal resistivity and reflectivity. However, only very few ablation and damage threshold studies at a wavelength of 13.5 nm are available up to now for these optical elements.

We studied 1-on-1 and 10-on-1 damage thresholds of Mo/Si multilayers with EUV radiation of 13.5 nm wavelength, using a table-top laser produced plasma source based on solid gold as target material. The experiments were performed on different types of Mo/Si mirror, showing no significant difference in single pulse damage thresholds. However, the damage threshold for ten pulses is ≈60 % lower than the single pulse threshold, implying a defect dominated damage process.

Using Nomarski (DIC) and atomic force microscopy (AFM) we analysed the damage morphologies, indicating a primarily thermally induced damage mechanism for higher fluences. Additionally, we characterised transmission and reflection properties of novel Mo/Si multilayer beam splitters performing wavefront measurements with a Hartmann sensor at 13.5 nm wavelength. Such wavefront measurements allow also actinic investigations of thermal lens effects on EUV optics.

My main takeaway from all of this is that even if the technical challenges of EUV make it ready for production for the 10nm device generation, there still must be lots of questions about the ultimate cost of ownership and how that will compare to double and triple patterning approaches with 193nm immersion.

For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing V_DD supply voltage as well as the subthreshold slope in transistors and optimizing multi-V_t  designs. Eventually, lateral finFETs built from silicon nanowires may be required. As previously reported in the post “Status update on logic and memory roadmaps,” the 14nm node (which imec calls the “N” node”) is in development today, heading toward early production in 2013/2014. That will be followed by the N10 node in production at the end of 2015 and beginning of 2016. Then N7 and N5 will follow in 2017 and 2019.

A detailed look at the likely roadmap for logic devices built on bulk silicon wafers using finFET technology was provided at the recent International Technology Forum for the press at imec in Leuven, Belgium in October. An Steegen, senior vice president process technology provided the overview, highlighting research underway for the 10nm, 7nm and 5nm nodes.

Steegen said power was a concern in both high performance logic devices, which are thermally limited, and in mobile devices, which are battery limited. “What we’ve been trying to do at all our technology nodes is to try to step down that power curve, mainly be trying to lower the V_dd,” she said. The trick, she said, was to lower the power, but still retain performance, and the best way to do that is to make the subthreshold slope of the device steeper. She said the target was 16mv/decade, which is the limit of conventional transistors.

There’s a tradeoff, however, in that reduced V_dd often means increased variability, depending on the threshold voltage of the devices. “On the High V_t device, when you go low Vdd, you’re so close to the threshold voltage of your device that the spread becomes enormous. What you could do is switch to a low V_t device. That’s better for variability but your leakage is going to increase,” she said.

At imec, their research is focused on bulk silicon finFETs (others are exploring fully depleted SOI) with a replacement gate and high k. Work is still underway on ways to best integrate a replacement metal gate, and on multi-V_t devices. “That’s still work we are executing,” she said. She noted that imec has worked on high-k metal (HKMG) gates for more than 15 years, and is now looking at how to implement a replacement metal gate on a finFET device and enginner the V_ts. “Uou also need to make sure your reliability comes together,” she said.

One way in which they have enabled multi-V_T tuning (range up to 600mV) is with controlled Al diffusion in metal gate stack. “You want to make sure you can offer the designers a low V_t device, a standard V_t device and a high V_t device, which means that you need to be able to tweak the materials in your gate to cover that entire range of V_t scaling,” Steegen said.

She added that, for the 10nm node, they are engineering an entire silicon finFET platform. “That means we work on every single module going in, from scaling to the N10 dimensions, control of the fin height, making sure you get conformal doping in the fin, and source/drain engineering because you still want to get some form of stress from your source/drain.”

For the 7nm node, Steegen believes the channel materials will need to be replaced with higher mobility materials, germanium for PFETs and InGaAs for NFETS. To integrate these materials, a technique known as Aspect Ratio Trapping (ART) is used. This technique uses high aspect ratio sub-micron trenches to trap threading dislocations, greatly reducing the dislocation density of lattice mismatched materials grown on silicon. “You have engineer your dislocations and defects,” Steegen said.

ART is shown to be very effective for a wide variety of materials including Ge, GaAs and InP. It has been combined with epitaxial lateral overgrowth to create long, 18 micron wide strips of low dislocation density material. ART has been used to integrate many types of Ge and III-V devices on silicon including GaAs MOSFETs, GaAs lasers, GaAs tunnel diodes and a silicon infrared imager chip with monolithically integrated Ge photodiodes.

For PFETs, the technique involved, “recessing the silicon, growing silicon germanium buffer back and then strained germanium on the top. The STI is then going to be recessed and you have a strained germanium fin on the top,” Steegen explained. The same integration scheme is used for NFETs, but “it’s a little more complex to try to get to a strained InGaAs NFET channel because the lattice mismatch with silicon is larger. You have to use more buffers here and go a little bit deeper to grow all these buffers through the trench,” she said. “Aspect ratio trapping makes sure all the defects — and you’re going to have them in that strained/relaxed buffer — are trapped at the sidewalls of the STI so that they don’t reach the top silicon.”

This added complexity appears to be worth the effort based on modeling, which shows a net gain of 25% more performance at constant power, compared to a bulk silicon finFETs. “There is still a lot of benefit you’re going to get in one node by replacing these channel materials,” Steegen noted.

Beyond 7nm, imec is looking at higher mobility materials such as graphene, and also looking at new device architectures such as tunnel FETS. “At this point, we are looking at germanium source tunnel FET to overcome the tunneling barrier with a lower bandgap material at the source,” Steegen said. “We truly want to try to break that 60mv/decade subthreshold slope.” She said lots of progress has been made but there was more work to do to understand band-to-band tunneling mechanisms. The team is also looking at “2D” materials such molybdenum disulfide and tungsten diselenide.