NEC opens doors of new R & D fab

NEC opens doors of new R & D fab

By Christine Lunday

Sagamihara, Japan — Japanese chip giant NEC has formally opened its new semiconductor R & D facility, at its plant in Sagamihara, outside Tokyo. Known as the UC Plant, the facility is designed to handle process development for geometries from 0.18 to 0.07 micron over the next decade.

NEC said it plans to start production of 0.18 micron logic devices by the beginning of 1999, 0.15 micron logic by the beginning of 2000, and 0.13 micron logic by 2001 at the new fab. The company`s DRAM roadmap calls for manufacturing of 256-Mbyte devices in 1999, sampling of 1-Gbyte devices at the beginning of 1999, and sampling of 4-Gbyte chips in 2001.

The UC Plant is based in a six-story building, with the UC6 processing line on the top floor. It has a current capacity of 3,000 200 mm wafers per month; this will rise to 5,000 wafers per month when fully equipped. In the first phase of work, research will cover such areas as lithography using 248 nm, 193 nm, and e-beam techniques; interconnect using copper and tantalum pentoxide as well as low-K dielectrics; and a high-speed transport system and CIM technology to reduce cycle times. The line will run both R & D and pilot production, to speed transfer of processes into manufacturing. A co-generation system and fan filter unit air conditioning are designed to reduce energy consumption; better water recycling and waste collection are also incorporated.

Individual 300-mm machines will be installed on the floor for evaluation and basic process development starting this year; NEC currently expects to begin volume 300-mm production in 2000 or 2001. In the facility`s second phase (slated for the 2000 time frame), a full 300-mm/0.13 micron process line will be installed. In about 2003, a 0.07 micron line will be put in place.

Investment for the first phase was 50 billion yen (about $357 million); total spending over 10 years is pegged at 200 billion yen. Total floor space in the building is 25,000 square meters, including three 6,500-square-meter cleanrooms on different floors. CR

Articles written by Christine Lunday are reprinted from WaferNews, a weekly newsletter published by PennWell covering the semiconductor equipment and materials community. For information on subscriptions, check the web at, or contact Jill Wood at 603/891-9174, fax 603/891-0597, or e-mail [email protected].


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