Equipment makers lead the charge in 300-mm shift
By Tammy Wright
Austin, TX — As the semiconductor industry ponders the transition to 300 mm, experts say larger substrates and shrinking geometries mean lower defect tolerances and more emphasis on contamination control measures. Part of the responsibility for the shift, they believe, will fall on equipment manufacturers, who must upgrade 200-mm technology to meet the increased cleanliness requirements of next-generation wafer production.
“Such small levels of contamination are issues for [particle] monitoring companies and point-of-use delivery systems,” contends John Schuler of SEMI`s market statistics department. Schuler identified some of the challenges surrounding the delayed 300-mm transition during a market briefing at Semicon Southwest `98 held in October in Austin. He sees an emerging trend toward full robotics and increased usage of minienvironments.
The 300-mm issue, however, is more complex than just utilizing robots and containers, according to Ahmed A. Busnaina, Ph.D., professor and director of the Microcontamination Research Laboratory at Clarkson University (Potsdam, NY).
Busnaina, who taught a course on surface cleaning at Semicon Southwest, believes that process modifications and process improvements related to polishing, manufacturing and cleaning are key areas of consideration in the 300-mm transition. He says “everything” will have to be scaled depending on the substrate size and circuit line widths that chip manufacturers choose to go with.
“Most likely, 300 mm will have smaller feature sizes so manufacturers will have [to deal with] smaller particles. For [300 mm with] advanced feature sizes, they will have to improve clean processes,” explains Busnaina.
Unlike the 200-mm transition, which was primarily funded by IBM, Busnaina says equipment manufacturers are shouldering 300-mm research and development.
“When IBM went from 5- to 8-inch wafers, it paid a lot of money for tool development and then companies turned around and sold the equipment to other manufacturers,” he says. “People don`t want to make [IBM`s] financial mistake.”
To date, industry analysts estimate that equipment manufacturers have spent about $4 billion on 300-mm research and development, with Applied Materials, Tokyo Electron (TEL) and Nikon Lithography routinely cited among the top five investors.
“Those companies have invested intensely [in 300 mm]. They`re representative of an enormous upfront investment that is now on hold,” says Kerry Kiser, 300-mm project manager at Chaska, MN-based Fluoroware Inc., a global supplier of materials management solutions for the semiconductor and other mission-critical industries.
Kiser — who has been involved in strategy planning for 300 mm with both Fluoroware and his former employer, Intel — says industry, led by Intel, took the position that no NRE (non-recurring engineering funding) would be available for the transition. As a result, chipmakers and suppliers worked together to develop SEMI standards for 300-mm carriers and load ports, which provided suppliers with a model for tool development.
“There`s been a concerted industry effort around the standardization of 300-mm equipment that wasn`t done for 200 mm,” Kiser adds. “For something as critical as carriers, standardization provides IC makers with a commoditized model [at a lower cost], yet it doesn`t [dictate] full product specifications, which leaves room for some innovation.”
To combat the smaller particles and greater number of contaminants associated with 300-mm manufacturing, Kiser says equipment makers are utilizing isolation technology and automation. He says next-generation wafers will be processed through front opening unified pod (FOUP) carriers and automatic load ports that attach to the front of process and metrology tools.
In present-day 200-mm fabs, wafers are transported by humans from tool to tool in open cassettes in clam-shell boxes, which expose them to Class 1 air when opened, or in rare instances, they are transported by humans in standard mechanical interface (SMIF) pods, which locally isolate the open cassettes and control the air surrounding only the wafers.
“With FOUPs, we`ve modernized the SMIF pod idea so that every 300-mm FOUP is its own minienvironment. They`re automation-friendly and they keep wafers horizontal so you don`t have to do rotations,” Kiser says, pointing out that IC makers in the U.S., Europe and the majority of Japan have adopted the FOUP concept. He claims the only holdouts are NEC and Mitsubishi, two Japanese companies who prefer to maintain the use of open cassettes. (CleanRooms, January 1998, “Majority of Japanese chipmakers choose minienvironments,” p. 1).
FOUPs, however, are more effective as a first line defense for particle contamination since they control the area around the wafer instead of the whole fab, according to Kiser. That`s critical, he contends, because smaller design rules translate into smaller particles, which can cause yield defects.
FOUPs are also expected to help combat airborne molecular contamination (AMC), another yield destroyer affecting design rules 0.18 micron and below.
“Cleanrooms are designed to filter particles, not these gaseous molecules,” explains Kiser. “The prediction is that as we go to smaller geometries, AMC looks like a huge issue, not an inconvenience. This means that FOUPs are the perfect barrier for AMC as well as particulation.”
Another technology in the works is gas purge, where two or four valves are located on the bottom of a SMIF pod or FOUP. Once the door is closed, clean air dry or inert gas is injected and resident or ambient gases are pulled out. Kiser says its exact implications are not yet known, but it`s a hedge against humidity and oxidation, which can be corrosive elements in some processes.
“It`s a next line of defense, an insurance policy people are talking about,” he notes.
At present, suppliers are waiting for IC makers to commit to building 300-mm fabs. When that happens, Kiser believes 300-mm facilities will start out as Class 1 fabs with minienvironment tools and FOUPs.
At some point, though, he says industry will “start turning down the wick” because 300-mm technology will allow IC makers to maintain the appropriate cleanliness levels in isolated areas and lower the specs for the entire fab.
“I`ve seen studies that report cost savings first start to show at Class 1,000 levels,” Kiser notes. “But, going to a blue jean or class-ambient fab is a progression.”
To keep the wafer business moving ever forward, industry is continuing to anticipate problems that could be associated with future manufacturing. Busnaina says he recently participated in an invitation-only workshop sponsored by Sematech that discussed 0.05 micron particles; SEMI has updated its 11-volume set of standards, which include 300-mm installation guidelines; and SMIF isolation pioneer Asyst Technologies just formed a new automation group charged with delivering complete fab/interface solutions to OEMs and semiconductor manufacturers worldwide, including robotics, minienvironments, software, auto identification and load port transfer interfaces.