“The operators complained that papers don't stick to partitions anymore,” recalls Andy Rudack, a lithography manufacturing development equipment engineer who works in Sematech's (Austin, TX) 193 nanometer Resist Test Center. The center focuses on developing the technology needed for the next generation of semiconductors.
Ion Systems Inc. (Berkeley, CA) donated static suppression equipment, which Sematech installed in the center. As a result, the charge on walls and other surfaces plummeted, in some cases by tens of thousands of volts. A series of experiments are underway to evaluate the effect of the static charge reduction.
Those static-free dividers may be something cleanroom workers have to live with. Sematech is engaged in these static reduction experiments because charge buildup is suspected of degrading yields, lowering throughput and hindering advanced processes.
The downside of going small
A semiconductor cleanroom is an excellent static generator. In an advanced process, there's ceiling-to-floor laminar flow that moves a great deal of relatively dry air over surfaces. What's more, many of the materials used in semiconductor manufacturing are selected for two reasons. Of primary importance is that the materials don't shed particles and that they can withstand the harsh chemicals used in manufacturing. The ability to dissipate charge frequently doesn't enter into these considerations.
As the air flows past surfaces, or wafers move into and out of carriers, or operators walk around, the result is tribocharging. Because this happens constantly, static builds. Because the materials, including semiconductor wafers, either aren't grounded or don't dissipate charge, voltage levels can be quite high.
Carl Newberg, president of the static control concern River's Edge Technical Service (Rochester, MN), regularly visits cleanrooms and takes readings of the static levels of various surfaces on such objects as air deflectors. He does so using a meter with a 20,000 volt upper limit. Newberg says such measurements peg the meter, indicating readings beyond the upper limit.
Eventually, this charge can lead to electrostatic discharge (ESD). ESD arises when static dissipates in a sudden burst, sometimes striking like miniature lightning. Any conductive path to ground is a candidate for ESD, and one of the places it can go is through the semiconductor wafer itself.
“You can discharge to the die structure of a wafer, and that can cause material degradation,” says Thomas Albano, an electrostatic control engineer with Kodak and also chairman of the Clean Manufacturing Guidelines for Electrostatics group within the ESD Association.
Static buildup and discharge have been present in cleanrooms from the beginning. What has changed is that advancing semiconductor technology is making the problem more acute. Traditional semiconductor ESD solutions have relied on protection through circuit layout and design. But shrinking dimensions mean that such protection circuits have less and less margin. In particular, the thinning of transistor gate oxide and the shrinking of transistor junction areas narrow the design solutions. That has an impact on the manufacturability of a semiconductor device both inside and outside of the cleanroom.
“Since the design solution space is very narrow, it is conceivable that you end up with a device that meets all of your performance requirements, except it can't take any ESD current whatsoever,” notes Koen Verhaege, group head of device design at the Sarnoff Corp. (Princeton, NJ).
Verhaege, who develops device structures to handle ESD, thinks that static discharge protection will eventually have to be considered during process development. He cites the 1 micron process generation as the point where these ESD problems first began to be really noticeable. The upcoming 0.13 micron process generation has such high ESD susceptibility, says Verhaege, that some changes to basic design rules may be necessary just to be able to successfully manufacture ESD-resistant devices.
Static cling and mousebites
Shrinking device sizes magnify the static charge contribution to contamination in several other ways. For one thing, although a cleanroom is clean, it isn't spotless. There are some particles present. For semiconductor wafers, the combination of static and particles can be troublesome. This is particularly true in advanced processes, where feature sizes are less than 0.3 micron. That's because a static charge attracts particles and makes them stick, but it doesn't do so uniformly for every particle size.
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“Attraction goes up at the smaller particle sizes. For a number of reasons, there's an actual minimum in deposition velocity curve between 0.3 and 0.5 micron. If you're larger than that you get deposition caused by gravity. If you're smaller than that, you get it caused by static charge and diffusion,” notes Arnold Steinman, chief technology officer for Ion Systems.
This particle vacuuming contributes to two contamination problems. The first is that the static charge that sucks particles onto a wafer has to be dissipated. This ESD event can damage sensitive devices. The second is that the particles almost literally bond to the silicon surface. It is difficult to remove them, and so they cling through cleans and other processes. A distorted circuit pattern may result.
Both of these problems can lead to “dead” devices or the walking wounded, devices that function for a time but then fail. It's thought that both problems will grow worse as device dimensions shrink.
Turning wafers into particle magnets is bad enough, but at least the damage, if any, is confined to a single semiconductor die. The same can't be said for ESD events that affect reticles, the chrome-laden master circuit patterns. In photolithography, light is used to transfer the reticle pattern to device die on a wafer. Because a reticle is used repeatedly across many die and wafers, a reticle defect has the potential to maim or kill many devices.
According to Rudack of Sematech, experiments are underway to measure both particle deposition on wafers and reticles. The wafer tests consist of cycling wafers through equipment, with static suppressing air ionizers on and off. After multiple passes, particles on the wafers will be counted.
For reticles, the plan is to subject them to multiple equipment passes, again with ionization on and off. Instead of particles, the researchers will look for “mousebites,” missing chrome that results from an ESD event. The arc that dissipates the charge also vaporizes the chrome.
It's thought that this problem also will grow worse as feature sizes shrink. One reason is that while the width of a given circuit trace diminishes, the length does not. This is because die dimensions are growing even as feature sizes shrink. According to the 1997 National Technology Roadmap for Semiconductors, the 0.13 micron generation of die will be 50 to 100 percent larger per side than the 0.25 micron generation. Longer, more densely packed chrome runs will mean an even greater chance of mousebites.
Steinman of Ion Systems notes that there are reports that these long, thin chrome runs are experiencing a new kind of ESD damage. Instead of a catastrophic failure, there are defects that grow over time as more and more ESD events occur.
Preventing various breakdowns
Another area that Sematech is investig ating has nothing to do with cleanroom contami nation per se, but it does have a lot to do with man u facturing through put. In today's semiconductor clean rooms, com plex ro bots handle wafers. Those robots load and unload silicon into processing tools that are equally, if not even more, complex. All of these machines have microprocessors and a significant amount of wiring.
Newberg of River's Edge Technical Service recalls one fab where ESD events weren't just harming the silicon. They were affecting those robots and tools, as electricity arced from charged wafers to grounded equipment.
“The equipment would latch up, and they would have to reset it,” he remarks.
Rudack of Sematech says ESD events produce fleeting 300 – 500 megahertz radio signals. John O'Reilly, semiconductor sector manager for Ion Systems, comments that an antenna and a digital oscilloscope will detect such signals in any semiconductor cleanroom in the world.
If this electronic noise happens at the right time in a microprocessor's execution cycle, the result is a confused machine. The machine locks up, and then has to be reset, as Newberg noted. These machine malfunctions tend to be intermittent and of short duration. Both Newberg and O'Reilly note that often the problem is invisible to senior management, because the equipment operators correct the problem on the manufacturing floor. Nevertheless, such lockups are a loss in throughput.
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These ESD-induced elec tronic nervous breakdowns, if they happen, won't be confined to semiconductor cleanrooms. Any complex piece of equipment could potentially experience the same problem.
Finally, there is the impact of static charge on advanced manufacturing. In Sematech's case, investigations are underway to determine whether static affects the delicate process of photolithography. The most advanced photolithography requires that exposure and development take place in an isolated environment. Trace airborne chemicals used in other areas of semiconductor manufacturing will cause problems. Indeed, these airborne contaminants will halt the resist development process. Instead of vertical features, for instance, there may be mushrooming, where the top balloons out. It's thought that static may contribute to this, but Rudack, for one, isn't sure that this is the case.
However, one sure thing is that silicon isn't the only semiconductor. Gallium arsenide, for example, is a compound semiconductor that is widely used for wireless communications. These non-silicon semiconductors face their own, special ESD problems.
“Static suppression technology is up to the task for ESD protected areas following the present standards. But this still allows 100 volt static charge to built up. Most compound semiconductors are damaged at much lower voltages,” says Karlheinz Bock, coordinator of the ESD group at the Interuniversity Micro Electronics Centre (IMEC) in Leuven, Belgium.
Bock points out that the silicon-on-insulator processes under development by various companies may also be more prone to ESD damage than standard silicon processing.
Wiping static clean
Unfortunately, the options are limited as far as preventing ESD in a semiconductor cleanroom. The required level of cleanliness means that a certain air flow has to be maintained. The need to complete some complex chemical reactions means that the humidity of the air has to be controlled. So, one of the ways to eliminate static, high humidity, is not available, and the flow of air can't be slowed.
“I think the best control that you can do is to keep the insulative materials out of the clean- room,” says Jay Hamlin, a staff engineer with Qualcomm Inc. (San Diego, CA). Hamlin worked on ESD at both Intel and Motorola. He's also been active in the Southern California chapter of the ESD Association.
There are challenges in this approach. For one thing, cleanroom materials must be clean. Some also have to withstand acid baths without degradation. So, materials can't bleed off charge at the expense of cleanliness and robustness.
There's also the problem of providing a path to ground. For robots and such, this can be done through a wired connection. For wall panels, Plexiglas partitions and the like, conductive paint or a wire can be used. For cleanroom garments, the only solution is to provide contact from foot coverings through paint on the floor. However, as Hamlin notes, the quality of the electrical contact of such a contact to ground varies.
Then there's the problem of consumables. What is to be done with such things as cleanroom gloves and wipers?
Creighton Kelly, a technical director of the fabricating business at Milliken and Company Inc. (Spartanburg, SC), is chair of the Institute of Environment Sciences and Technology (IEST) working group four, which is evaluating wiping materials.
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“Just the movement of a wiper through the air will create a significant amount of charge. That is said to be the most sensitive in the disk drive industry where 500 to 5,000 volts will totally dismantle an MR head. You can generate that voltage just by moving a wiper about two feet into an air stream that does not have proper ionization,” he says.
To overcome all of these hurdles, some advocate the use of ionization. By flooding an area with both positive and negative ions, any charge can be suppressed. There's no need to alter materials or worry about the quality of electrical contact to ground. However, Albano of Kodak says that whole room ionization is tricky. In particular, highly conductive surfaces, such as metal walls, may act as ion sinks. The ions will strike the walls, be absorbed and disappear. That limits the effectiveness of ionization elsewhere in the room, and so whole room ionization may not be enough.
“You have to actually look at your process equipment. Ionization is not effective if you don't have exposure of your media or items within your process equipment. So then you have to go to point-of-use ionization,” comments Albano.
That is what Sematech is doing with its series of experiments. In addition to whole room ionization, the research consortium plans to look into ionization inside tools. Rudack expects to have preliminary results by the end of the summer. He's sure that some aspects of the tests – such as those that involve particles – will show improvement under ionization. Others, such as the impact on advanced processing, will be more of a toss-up.