CSP and Flip Chip Packaging
A comparison of market and technology trends.
STEVEN J. ADAMSON
Although wire bond technology continues to dominate the integrated circuit (IC) packaging market from a volume standpoint, over the past few years most of the industry “buzz” has focused on the increasing use of leading-edge packaging techniques, such as chip scale packaging (CSP) and flip chip. Despite that they represent a small portion of the overall packaging volume, most industry analysts have been predicting very rapid growth rates for CSP and flip chip because, ultimately, they represent the most viable path for achieving tomorrow`s high-density interconnect requirements.
Electronic Trend Publications predicted that CSP usage will grow from its 1997 level of 158 million units to more than 1 billion units in 1999 and will reach approximately 3.9 billion units in 2002, representing a very robust 90 percent annual growth rate. Similarly, Prismark Partners has estimated that the number of flip chip units increased by 40 percent during 1998 to a total of 899 million units.1 While the combination of CSP and flip chip volumes still comprises only 2 to 3 percent of the more than 60 billion ICs produced annually, it is clear that these newer technologies will pull significant market share from traditional wire bond methods over the next few years (Figure 1).
However, even these current growth forecasts for flip chip and CSP represent something of a scaling back from the extremely bullish predictions of just a few years ago. As with many new technologies, where the initial optimism outstrips practical implementation considerations, both flip chip and CSP have undergone a significant maturation process to prepare for production environments. The need to invest in new equipment and methodologies has also tended to make many IC manufacturers opt for squeezing the maximum results out of their existing wire bond techniques before changing over to new technologies.
In addition, the introduction of flip chip on board (FCOB) appears to have been deferred because some manufacturers focused on CSP implementations as a potentially easier transition, but they later reconsidered as they encountered unanticipated production and design challenges.
This article takes a closer look at the trade-offs between CSP and flip chip applications. It also addresses some of the key processes, such as underfill dispensing, that have helped make both CSP and flip chip technologies more robust and production-ready.
Assessing the Trade-offs Between CSP and Flip Chip
Many manufacturers initially viewed CSP as a “softer entry” than jumping directly into flip chip because much of their existing surface mount equipment could be transitioned to CSP. Because the task of putting a CSP package on to a standard FR-4 PCB assembly was essentially the same as any other surface mount technology (SMT) component, CSP represented a very attractive interim step that did little to disrupt the eYciency of mature SMT production lines. Also, because the definition of CSP calls for approximately 1.2 times the size of the die itself, it was close to providing the densities achievable with flip chip, while simultaneously allowing for more latitude in the board-level processes being used.
From a cost and diYculty standpoint, controlling the quality of a small CSP interposer substrate was considered to be significantly less daunting than the challenge and expense of controlling the substrate characteristics and precision microvias for placing a flip chip directly on the printed circuit board (PCB) assembly.
According to the National Electronics Manufacturing Initiative (NEMI), organic PCBs account for more than 90 percent of today`s interconnecting structures, with FR-4 representing 85 percent of the resin system used to produce copper clad laminate.2 Current organic PCB technology has climbed the volume curve and descended the cost curve to the point where it is viewed as a bedrock technique that should be leveraged rather than displaced or disrupted.
Additionally, when it comes to the layout of interconnects, CSP allows for significantly larger circuit trace and spacing dimensions than FCOB, thereby making it more compatible with existing state-of-the-art PCBs in the 100 mm range. However, cost of a PCB substrate could be significantly increased by laser drilled microvia technology and 50 mm to 75 mm trace dimensions that are typically required for FCOB applications.
Initially, there was also a widespread belief that the more controlled substrate conditions and larger solder ball dimensions in CSP would provide the required mechanical stability, thereby avoiding the need for using underfill processes. Because CSP solder ball heights are approximately 12 mil vs. 3 mil for flip chip, early CSP designers knew that the solder ball structure itself could handle the mechanical strains associated with thermal expansion of the substrate and die. However, subsequent information has shown that, as protection against mechanical shock, CSP reliability needs to be significantly enhanced through the use of underfill. Therefore, the effective use of underfill dispensing plays a key role in CSP and flip chip applications, but for different failure mechanisms.
High Densities Increase Flip Chip Usage
Over the past few years of real-world experience, manufacturers have painfully discovered that CSP is not just a “drop in” on their existing SMT lines, but it requires a learning curve, process adaptation and new equipment investments associated with any major new technique. At the same time, the relentless push toward greater densities has also driven manufacturers to apply their newfound knowledge and make the full jump to flip chip.
For most new consumer electronic products, higher densities have been accepted as a fact of life as form factors become smaller and functionality increases for cellular phones, pagers, digital cameras, hand-held computers and other high-volume consumer items. In many cases, CSP designs are so tight that the die are nearly touching with virtually no spare real estate left on the board. As a result of this continued march to higher densities, the industry is now shifting to view CSP as just a “step on the way” to flip chip technology, with a useful life of five to seven years.
Optimization of Dispensing Processes
Even though in the long term, CSP may be viewed as a transition technology, from a process standpoint, it is vitally important to harvest everything that has been learned to date in order to effectively apply the best techniques to meet the ongoing challenges of process control and optimization. For example, accurate dispensing of encapsulant underfill has become a key component in the reliable manufacture of CSP and flip chip devices. Over the past few years, leading dispensing system suppliers and fluid formulators have worked closely with flip chip and CSP manufacturers to evolve and improve processes, such that today`s dispensing capabilities have already progressed to a third generation of refinement.
For example, flip chip in package designs, such as ball grid arrays, have already driven dispensing techniques to a high level of sophistication and process control to achieve consistent underfill beneath the die, while avoiding either voids or material overflow. In flip chip underfill applications, precision control becomes a concern because the dispensing needle has to move close to the chip throughout the process. The needle must be positioned far enough from the chip to avoid back-side contamination but close enough to promote capillary flow of the fluid under the chip. In addition, the dispensing pattern must be carefully designed to optimize flow-out under the chip while maximizing throughput.
Although throughput considerations often require dispensing on multiple sides of a chip in a single pass, extreme care must be taken to manage the flow-out directions of multiple wave fronts that are created under the chip. The angle of intersection between multiple wave fronts can be a major factor in the creation of voids. By controlling the dispensing pattern so that the wave fronts merge at an oblique angle of <90°, the likelihood of voids can be significantly diminished. However, if opposing wave fronts meet at an acute angle of >90°, the risk of creating voids is greatly increased.
In CSP`s early use, it was not clear that underfill encapsulation would become a significant requirement. However, real-world empirical experience and increasing densities have led CSP manufacturers to incorporate underfill as not only an added guard against the risk of damage from thermal fatigue, but primarily for reducing mechanical stresses. Also, the use of underfill for CSP designs has become a universal requirement in portable products. With many multichip module CSP applications, the underfill process must face the additional challenges of accurately dispensing under and around multiple devices that are closely packed. As a result, dispenser robotics, vision recognition systems and pump accuracy become paramount considerations in addition to thoroughly understanding the rheology of the underfill fluid being dispensed.
When dispensing to multiple CSPs on the same substrate, the process must be carefully designed to control the placement of the underfill fluid and its flow throughout the dispense cycle, taking care to underfill just the package currently being dispensed. Closely spaced passive chip components adjacent to CSPs can rob the underfill material away from the CSP through capillary action (Figure 2). However, in cases where other nearby components do get covered with underfill adhesive, no deleterious effects occur to the components.
There are other process advantages to dispensing underfills for CSPs. The underfill flow-out time is shorter. Since the space between the CSP and substrate is three to five times greater than a flip chip, the flow-out time is five times faster. Also, because the primary function of the CSP underfill is mechanical enhancement, the underfill fluids may be less expensive and voiding under the CSP is less problematic. As in FCOB underfilling, precision positioning and movement of the needle at high speed, as well as accurate and consistent control of the fluid flow throughout the process, are prerequisites for successful underfilling
In some very high-density designs, manufacturers are increasing packaging density by assembling flip chip die on the face of larger wire or tape bonded die. The underfill dispensing process used to fill the void between these two die demands exacting control of a few milligrams of dispensed fluid. Small diameter dispensing needles are required because only a small shelf area is available to receive the underfill fluid, which is not allowed to spill over the edge of the die. The small needle can lead to large pressure forces in the dispensing chamber, and it is very important to have an equipment manufacturer who is on a third generation of underfill pumps and understands the requirements for this type of process.
An emerging technique for use in FCOB applications is known as “no-flow underfill,” which can have significant advantages in terms of overall throughput, especially if flow-out times are high. The other advantage is to eliminate the adhesive cure cycle. In no-flow applications, the underfill is dispensed directly onto the substrate landing site, after which the chip is placed through the underfill under force to make electrical contact between the solder bumps and substrate pads (Figure 3). The assembly is then heated to reflow the solder and cure the underfill. Ultimately, the no-flow underfill material is designed to act as a flux during the process and a structural element after completing the process. The no-flow technique calls for the material to change from an acid-based flux into a polymer during the reflow and curing process. However, it has been reported that, in some formulations, not all of the acidic material is converted to neutral polymer chains, leaving a slightly acidic material in contact with the die face, which is not desirable.
No-flow materials do not have filler particles in the fluid, which could interfere with the solder ball reflow process. Therefore, their thermal coeYcient of expansion is larger than the capillary flow fluids. Consequently, high input/output flip chips may not benefit from the process because they require filled underfills for reliability. Once the no-flow materials are perfected, this process alternative can have significant throughput benefits for FCOB applications because it can eliminate the time required for the underfill to flow out beneath the chip. In addition, because the dispensing process has unrestricted access to the landing site prior to die placement, the no-flow process opens up future possibilities for using jet dispensing as a faster alternative to needle dispensing.
Summary
Over the past few years, many manufacturers have come to view CSP and flip chip as alternative or competing technologies, with CSP more closely meshing with traditional SMT processes and flip chip representing a more radical alternative.
With just a few years of hands-on experience, the industry has learned from the initial diYculties with controlling production methods, achieving acceptable yields and coming up the learning curve of new technology. Those manufacturers and equipment suppliers who have also focused on CSP and flip chip production have made great strides to refine the core processes required to achieve effective results. In addition, many manufacturers have already invested in laying the foundation of equipment and processes that can be used for CSP in the short term and transitioned to flip chip in the longer term. As a consequence, both CSP and flip chip techniques have gained significant benefits from the “cross-pollination” of process improvements and are now poised to actually achieve their predicted growth forecasts while giving manufacturers a set of powerful new methods for achieving improved circuit densities.
References
1. Charles L. Lassen, “Advanced Packaging Applications, Markets and Trends,” Semicon West, July 14, 1999.
2. Ronald Gedney and Jack Fisher, “The Future is Organic Substrates,” PC Fab, August 1999, pp. 28-31.
STEVEN J. ADAMSON, semiconductor packaging and assembly product manager, can be contacted at Asymtek, 2762 Loker Avenue West, Carlsbad, CA 92008-6603; (760) 431-1919; Fax: (760) 918-8332; E-mail: [email protected].
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Figure 1. Global consumption of flip chip devices.
(Source: Prismark Partners LLC.)
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Figure 2. Components oriented at 90° to the underfilled part will draw fluid away compared to chip components situated parallel to the underfilled component, which tend to act as a dam to fluid flow.
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Figure 3. Flip chip being pushed through no-flow underfill.