SUNNYVALE, CALIF. – Tru-Si Technologies Inc., a leader in atmospheric downstream plas- ma (ADP) processing for vertical miniaturization solutions, has announced a breakthrough overcoming the challenges that threaten Moore`s Law. Using its ADP etching process, the company has discovered a method of successfully stacking multiple chips by stacking wafers containing dif- ferent circuit functions, such as memory, logic, analog and digital. This technology, which maintains the economies of scale inherent in processing whole wafers, provides through-silicon vertical interconnections between the front and back sides of a wafer in a manner similar to that of through-holes in printed circuit boards. The result is a new concept in three-dimensional stacked wafer level packaging (S-WLP) and a new, three-dimensional Moore`s Law.
According to semiconductor technology roadmaps, Moore`s Law, which states that approximately every two years, the number of transistors per chip area doubles, is confronting a serious front-end challenge. With area geometries continuing to shrink, it may not be possible to reduce feature size to the point where tens of atoms determine the device characteristics. As a result, device area shrink efforts may slow down progress and the doubling timescale of Moore`s Law could easily increase to well beyond two years within a few device generations.
So far, the primary technical obstacle to mass production of high-density, vertically integrated modules is the challenge of forming die interconnections within a vertical chip stack. The flip chip concept does not allow for interconnection of more than two chips. Wire bonding methods are limited to the number of chips that can be efficiently stacked and they require manufacturers to link chips over edges. The formation of over-edge chip interconnections, however, is not only lengthy and barely automated, it is also cost-inefficient for high-volume production, and not applicable for wafer level packaging. Lengthy chip-to-chip interconnections are generally outside of the silicon environment and present a performance bottleneck, in spite of the performance superiority of the separated chips.
Unless the miniaturization drive shifts its focus toward vertical miniaturization and integration, further investment in reducing feature size could generate diminishing returns. ADP technology offers a potential solution by circumventing the chip-to-chip interconnection bottleneck with a simple method of creating vertically stacked chips using vertically stacked, multiple wafers containing different functions.
Tru-Si creates through-silicon wafer-to-wafer interconnections in a simple set of steps. The first step is to form deep isolated metal vias (50 to 150 µm) on the front side of a wafer that are connected to appropriate layers of circuitry. The second step is to apply ADP damage-free thinning technology to remove silicon from the back side of the wafer, carefully exposing the deep through-silicon vias without any mask. The process allows for rigid through-silicon contacts (up to 50 µm) on the back side of a wafer; these back-side contacts offer flip-chip-type performance and can be directly bonded to another wafer or substrate without an extra bumping process.
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SEM of a back-side bump array fabricated by the process flow and a single top-side mask (top-side oxide, metal depositions and back-side ADP dry chemical etching are self-aligned).