Die Attach | Semiconductor Digest

Step 3

Four die attach methods – epoxy, eutectic, soft solder and flip chip – serve to attach the semiconductor chip to the package and meet the demanding functionality requirements of today`s advanced semiconductor devices.

WALTER GISLER

KENT CONNELL

In the package assembly environment, die attach is a critical process step. In simple terms, die attach is placing a die (which is presented on a wafer frame) onto a metal or organic substrate using either an epoxy, solder or eutectic process to hold the die to the substrate. The most commonly used type of die attach is epoxy, possibly used by 70 to 80 percent of manufacturers today. However, as the entire scope of packaging changes to meet increasing demands for higher accuracy, greater speed, the ability to handle small die, the ability to handle a variety of substrate types and the need to address technology challenges (such as 300 mm wafers), die attach is advancing.

Epoxy Die Bonding

The materials needed for die bonding are a diced wafer mounted on a wafer frame (using a tacky tape), lead frames or substrates to place the die on, an adhesive (epoxy or solder), bonding tools to pick up the die and place it on the substrate, and of course, a die bonder (Figure 1).

The main components of a die bonder are the wafer handling section, the lead frame handler or work holder, and the pick-and-place module. The die bonding process includes several fully automated steps as detailed below; some of these steps are performed simultaneously (Figures 2-4).

1. A stack of lead frames or substrates is placed into the lead frame loading module of the die bonder. The robotic lead frame loader picks up a lead frame from the stack and places it onto the lead frame handler or indexer.

2. Moveable clamps transport the lead frame from the input position to the first process position, the dispenser (either epoxy or solder, depending on the process).

3. At the dispense position, each bond pad on the lead frame is aligned using optics and precision sensors. An adhesive is dispensed in a pattern and volume appropriate for the chip size.

4. Lead frames and substrates contain multiple bond positions; adhesive is dispensed on each position sequentially.

5. Once the dispensing has been completed on the entire lead frame or substrate, it is transported along the indexer to the second process position, which is bonding.

6. While the lead frame or substrate is processed through dispensing, a diced wafer on a wafer frame is presented to the system and a chip is optically aligned and prepared to be picked for placement on the next lead frame or substrate.

7. The bond head picks a die from the wafer using a vacuum pick-up tool that grabs the die from the top, while a push-up mechanism from below the wafer gently releases the die from the tape.

8. Once picked and held on the bond head, the die is transferred to the bonding position where it is placed on the bond pad with the pre-dispensed adhesive.

9. At the same time the die is picked from the wafer, the bond pad is accurately aligned using optics and precision sensors.

10. Bonding time and bonding force results in a strong bond according to the specified process requirement.

11. Each bond pad on the lead frame or substrate goes through this process before the lead frame is unloaded into an output magazine.

12. Once a magazine is filled with lead frames or substrates, it is transported from the die bonder to a curing station.

There are also options available that enable optical dispense and bond quality checks. Because a number of steps are completed simultaneously, a very fast throughput is possible. A good rule of thumb in estimating throughput is one die attach per second. This results in an average of 3,600 uph. Typical throughput ranges from a high 7,000 uph for a small-outline integrated circuit (SOIC) device to a low of 2,200 uph for a singulated ball grid array (BGA) using epoxy.

Die Bonding Processes

The most commonly used processes in die bonding are epoxy, eutectic and soft solder bonding. Flip chip is an up-and-coming process.

Epoxy die attach: This process relies heavily on the performance of the materials being used, especially in the case of epoxy. There has been a tremendous evolution in the variety of available epoxies because of pressure to eliminate process steps (like curing), reduce cycle time and improve quality. Products using epoxy die attach include BGAs, quad flat packs (QFPs), plastic leaded chip carriers (PLCCs) and SOICs.

Eutectic die attach: Eutectic die attach places die onto a substrate without administering any separate adhesive. This is done by heating the metalization on the substrate, which transfers to the metalization on the back side of the die, forming an intermetallic bond. To achieve a strong intermetallic bond, a scrub motion is required during bonding. The die back-side metalization is typically gold. Not to be confused with eutectic processes using soft solder, this process does not introduce an outside adhesive or solder. Typically, heat is located within close proximity of the bonding area and requires a shorter heat ramp up/down cycle. A forming gas atmosphere (usually a nitrogen/hydrogen combination) is required to prevent oxidation on the substrate. Low power amplifiers are made using eutectic die attach.

Soft solder die attach: Soft solder bonding is a eutectic process, but it introduces a solder material to achieve the bond. These solders are typically lead and tin-based alloys. The solder is introduced either as a wire preform or through a liquid pattern solder dispenser. This process requires a much longer heat ramp-up and cool-down profile in the work holder than a “solderless” eutectic process. As with other eutectic processes, a forming gas atmosphere is required to prevent lead frame oxidation. Parts made using a soft solder process are used in automotive applications, high-power devices, such as transistors, and some radio frequency applications.

Flip chip bonding: Flip chip has been around for more than two decades but has only recently gained popularity. This process entails picking a chip from a wafer or other presentation method, flipping the die over, aligning the die and placing it on the substrate. The interconnects between the chip and the substrate are balls that have been placed on the die surface.

Important Considerations

In evaluating a die attach process, it is important to understand a number of factors that can impact the process performance and end-product quality.

Accuracy: Accurate die attach is becoming more critical as designers try to fit more circuits on a chip and shrink package size. To improve accuracy, the mechanics and electronics on the pick-and-place and indexer are tightly engineered using extremely stable materials.

Shrinking die: The ability to pick up a very small die is another significant challenge. Suppliers are tackling this problem by using leading-edge vision technology combined with intelligent software alignment algorithms, which can more accurately see the die.

Fragile materials: Materials, such as gallium arsenide (GaAs), can be difficult to pick up because of their fragile composition. One solution to this problem is to use a sophisticated bond head that enables better controlled touch down and force capability, combined with ever-evolving pick tools (needles, collets, etc.).

Substrate tolerances: Handling different substrates that come with a wide range of tolerances is another obstacle. Metal lead frames often have very tight tolerances, whereas organic substrates have much looser tolerances. Advanced vision capability enables accurate die placement in these various situations.

Dispense control: The smaller the die, the more critical it is to accurately control dispensing. One solution is to use dispensers that enable manufacturers to control the dispense volume in both writing and stamping or printing modes.

Die Bonder Manufacturing Trends

As technology progresses, die bonding must also change, and there are many interesting trends currently facing packaging and assembly that impact die attach.

Smaller packages: Packages are getting smaller in size to accommodate devices for small consumer electronic products, including cellular phones, laptops, personal computers and personal assistants. Chip scale packages, BGAs and memory devices are shrinking in terms of area and thickness (Figure 5). The goal is to achieve less expensive packages that are compact enough for small devices, while still offering a high level of performance. The performance issue, in particular, is driving new technologies, such as flip chip attach. Materials other than silicon are also being used more to meet such requirements. For example, fragile materials, such as GaAs, are required in communication devices because of enhanced characteristics with higher frequencies.

Stacked die and multichip modules (MCMs): Rather than having multiple integrated circuits (ICs) with various functions on a board, MCMs are created when multiple die with different functions are placed on the same module; this creates a sophisticated package with excellent performance capabilities. MCMs are typically made by placing the die on top of each other or right next to each other on the same module using epoxy and soft solder processes. The modules are used in a multitude of different applications varying from communications devices to power devices.

Improved accuracy: As package sizes shrink, the bond pad becomes smaller in proportion to the chip to save space on the board. Die attach accuracy is important and it can be complex to achieve. Also, as wire bond pitch becomes smaller, accurate die placement is required to enable an accurate and ultra fine pitch (50 µm or better) wire placement.

Speed: Market pressures are driving package costs down and, as a result, equipment suppliers are expected to provide improved performance machines, as die bond speed has a direct correlation to the cost of a package. The faster the machine, the lower the capital equipment depreciation cost is attributed to the package.

Wider bond range: To save on material costs and cut out unnecessary cycle time, many package designers specify substrates in array form (Figure 6). The result is a need for wider bond areas. This includes die bonding and other downstream process steps.

300 mm: At some point, front-end semiconductor manufacturers` use of 300 mm wafers will require packaging to accommodate the large wafer size. This poses a question of how to handle large wafers, while minimizing the footprint of the machine. Wafers this size will be very delicate, and handling them without causing damage will be an issue for die bonder equipment designers.

Looking to the Future of Flip Chip

There are several market factors driving designers to flip chip packaging and increasing the popularity of this process. With flip chip, there are no leads to the outside world, but rather the IC is connected to the substrate with solder balls on the active side of the die; therefore, the overall dimensions of the package are much smaller. This allows board designers to place more silicon in less area.

As Moore`s Law drives the need for more circuits on a chip, the number of interconnects increases and the ability to connect the chip with the outside world becomes more difficult because the size and pitch of the wire bond pads continue to shrink. Traditional interconnect technologies are limited with very high lead count devices.

The performance of a device assembled using a flip chip process is also quite fast. The signal moving between the substrate and the chip for the flip chip process can be up to 10 times faster than when using wire bonding.

Flip chip is the predecessor to an emerging technology in which chips are placed directly onto a board – called direct chip attach (DCA). While DCA is being used in limited numbers today, flip chip assembly leads to volume DCA production in the future.

Obstacles in switching to flip chip are based in a process that still is not completely understood. Traditional interconnect using wire bonding has been used in volume production for years and is well-proven and accepted in the industry. The cost of bumping is still too high and the cost of substrates is still high compared to traditional die and wire bond processing.

Currently, microprocessors use flip chip more than any other package. Other exotic packages, which have very high (800 or more) interconnects, also use flip chip.

Understanding the three basic types of die attach is essential for evaluating newer technologies such as flip chip and assessing how die attach impacts performance and yield.

WALTER GISLER, section manager of die bonding, and KENT CONNELL, vice president and general manager, can be contacted at ESEC USA Inc., 9830 South 51st Street, Suite B-111, Phoenix, AZ 85044; 480-893-6990; E-mail: [email protected] and [email protected].