SAN FRANCISCO, CALIF.
IBM Research has announced breakthrough results in developing a family of experimental high-speed computer circuits that run at test speeds up to five times faster than today`s top chips. The new circuits employ an innovative design called Interlocked Pipelined CMOS (complementary metal oxide semiconductor) to reach speeds of 3.3 to 4.5 billion cycles per second (3.3 to 4.5 GHz) using conventional silicon transistors, while dramatically reducing power consumption. IBM researchers estimate that chips made with IPCMOS circuits will require only half the power used by a standard high-performance chip.
“To meet continuing demand for performance, we`re going to have to look beyond simply making circuits smaller,” said Dr. Randall D. Isaac, vice president of systems, technology and science at IBM Research.
The key to the IPCMOS design is a distributed clock function. In computer chips, the clock paces the speed of the circuits; standard designs use a centralized clock to synchronize the operations of an entire chip, ensuring that all operations run at the same interval (cycle). The clock waits for all of the operations on a chip to finish before starting the next cycle, so the speed of the entire chip is limited to the pace of the slowest operation. To increase the speed, IBM researchers have decentralized the clock, using locally generated clocks to run smaller sections of circuits. The advantages of this locally generated clock are both speed and power. In terms of speed, faster sections of circuits are free to run at higher cycles without needing to wait for slower operations to catch up. Additionally, power requirements are reportedly reduced significantly because the distributed IPCMOS clocks send signals locally only when an operation is being performed. Centralized clocks, on the other hand, send a signal to the entire chip, and the synchronizing function can use as much as two-thirds of the total power consumed.
“Maintaining a synchronous clock across an entire chip becomes increasingly difficult as performance rises, and the clock itself can limit performance,” said Stanley Schuster, one of the researchers working on IPCMOS. “We believe this new design will help us overcome those problems in future generations of high-speed chips.”