A high-performance chip carrier provides a robust, complete, optimized flip-chip carrier solution.
By David Alcoe, Kim Blackwell and Eric Laine
During the past few years, there has been significant investment in flip-chip assembly, substrate and die bumping development. This investment is driven by semiconductor applications requiring electrical performance and increased connection density improvements. In retrospect, one could make a comparison between the packaging industry's drive to replace lead frames with solder ball grid arrays and the concept of flip chip replacing wirebonding. The ball grid array (BGA) packaging format provided reduced inductance while, at the same time, provided a higher interconnection density and, ultimately, a lower cost. Similarly with flip chip, the industry is replacing wirebond wires and their electrical parasitics with arrays of very small solder balls (bumps). There appears to be a significant anticipation by many within the semiconductor community that flip-chip packaging will ultimately reach and surpass the price parity of wirebond. With volume applications like microprocessors and digital signal processors adopting flip chip as a die attach technique, this is not an unreasonable expectation.
To respond to customer requirements, it is necessary to truly understand their needs and the market trends that drive them. Figure 1 shows the BGA market growth predicted for flip-chip packaging compared to wirebond. It can be seen that a larger percentage of flip-chip packages is anticipated. Flip chip is expected to become more widely used and dominate higher I/O device applications (Figure 2). The marketplace is expected to migrate to the capabilities offered by flip-chip die attach to accomplish high I/O packaging.
 Figure 1. Projected growth of flip-chip and wirebond components (data courtesy of Prismark Partners LLC). |
With increased capabilities offered by flip-chip packaging come increased demands on packaging technology. Ever-increasing circuit densities and higher signal counts contribute to greater thermal flux and total power. Despite considerable advances in cooling technology, the simple act of powering up a computer system remains a stressful experience for chips and packages. The fundamental dissimilarity of the mechanical properties of the chip and all that necessarily interact with it leads to stresses because of temperature changes. These stresses can be considerable and, in time, can lead to system failure because of fracture, fatigue and other reliability manifestations.
 Figure 2. Component usage by lead count, forecast for years 2000 and 2004 (data courtesy of Prismark Partners LLC). |
When comparing the needs of various applications (and associated package stresses) to the strengths of various organic flip-chip packaging technologies, there appears to be weakness at the high end. At the low to middle range of application needs, incremental improvements to existing flip-chip packaging technologies can be implemented with success. However, at the high end, there are substantial increases in projected high-performance packaging needs. To meet these needs, a new technology for high-end flip-chip packaging should address high reliability, high electrical performance, high signal count, and reasonable cost and ease of use.
Tackling New Technology
The need for an overall chip carrier solution, not just a complex laminate, led us to many considerations and decisions relating to usage and implementation. For example, it was desireable to have a full array of eutetic solder ball reflow connections for ease of design, assembly and high performance. Air cooling using a commercially available high-performance heat sink was chosen, again for ease of system implementation. The high-performance nature of the chip carrier design dictated relatively high complexity of the circuit card to which it is ultimately joined. Analysis of BGA pitch, wireout capability and overall system cost led to the choice of offering 1.27 and 1.00-mm pitch connection to a circuit card with a thickness up to 110 mil. These seemingly simple system usage choices influenced many future events in the development process, as the chip carrier was optimized from an overall system usage standpoint to meet the stated goals.
 Figure 3. Comparison of FCA bare die relative warpage after 150°C underfill cure, various laminates. Data modeled with 730-µm thick die. |
Within the high-end flip chip attach (FCA) arena, the most widely used packaging scheme has been the flip chip multi-layer ceramic (MLC) packages made of alumina in pin, ball, column and land grid array formats (PGA, BGA, CGA, LGA). Within this general packaging scheme, a variation of the substrate material is the glass ceramic substrate, which has a property of essentially chip-matched coefficient of thermal expansion (CTE). Each of these packaging concepts does a good job of reducing chip to substrate stresses and associated reliability problems (such as fatigue, underfill delamination, chip cracking) because of the relatively close match of CTE between the chip and carrier. It is well-known that ceramic chip carriers are quite flat and remain flat; the relatively high stiffness of ceramic provides low warpage and stability. For isothermal conditions, very little stress exists. However, this packaging concept places the burden of accommodating a large CTE mismatch between the substrate and a printed circuit board.
Adressing Fatigue: Assuming a solder connection is used, there will exist temperature-dependent shear strains in the BGA between the MLC package and the printed wiring board (PWB). There is a very predictable, finite fatigue life of solder ball and column connections, which is related to the distance to neutral point (DNP) of a solder connection's location. Based on years of experience and testing, it can be determined if this life is acceptable for the reliability objectives of an application. Column connections reduce stress and increase fatigue life, but at the expense of creep load capability. Ball connections may also include standoff enhancements and provide acceptable fatigue life for moderate thermal excursions. More recently, land grid array (LGA) compressive sockets have been introduced to provide a compliant connection between the substrate and PWB. These sockets typically require use of a stiff backplate, holes in the circuit card and a specially designed clamping system to maintain a substantial compressive load if many hundreds or thousands of contacts are present.
 Table 1. Comparison of flip-chip carrier wireability. |
Flexibility: Organic materials can offer a lower dielectric constant, but this accompanies reduced stiffness and increased CTE. The various mechanical properties of different packaging materials can have far-reaching consequences for reliability of the chip packaging system; more interdependence of the organic chip carrier reliability and its usage conditions is key. Organic chip carriers can have behaviors in apparent contrast to time-honored and now-obvious behaviors of ceramic packages. For example, BGA connections at the far DNP are not necessarily the most highly stressed connections in some organic package designs; flexibility of the materials is the reason why the chip influence can be more important. This flexibility is also the root of why system usage considerations are vital for most organic packaging. Warpage, because of CTE mismatch between the chip and laminate, is much more significant for organic packaging than ceramic (Figure 3). Structures that affect warpage of the overall system, such as card thickness, lid thickness and adhesive choices, heat sink usage, or backside components, also affect the state of stress of the chip carrier system and, therefore, affect reliability. A complete understanding of the mechanics of optimal package behavior, and influence of the system usage conditions, was necessary to successfully develop an organic high-performance chip carrier (HPCC).
Packaging Development
In developing a package with high electrical performance, a stripline format of signal, ground and power planes became necessary (Figure 4). There are two power planes surrounding a central ground plane; signals are sandwiched to obtain the stripline format. Two additional wiring planes and two mounting planes give a 4S3P laminate format. The need for many closely spaced (225 micron) chip I/O and desire for low inductance power distribution, to accommodate high switching rates, largely influenced the selection of full escape capability using plated through-holes. The physical size and spacing needed to accomplish this, coupled with plating process abilities, evolved into the use of 50 micron outside-diameter plated through-holes. These are laser-drilled with 212 micron pitch capability, through a total of approximately 380 micron of laminate materials. Minimum overall laminate thickness further contributes to good electrical properties. A completed HPCC is shown in overall cross section in Figure 5.
 Table 2. Status of reliability testing of 14.7-mm die /42.5-mm body/1657 I/O HPCC. Card format is a 110-mil test card with a 125 gram heat sink. |
Performance: The construction attributes, including low dielectric constant and loss material, thin profile, stripline signal distribution and vias for each C4 connection, allow for good electrical performance. Impedence is tightly controlled to 55 ohms nominal. Power and ground loop inductance and time of flight are low and the resistance inductance capacitance (RLC) parasitics are good. These characteristics are enabled through the use of the polytetrafluoroethylene (PTFE) dielectric material, with a dielectric constant of 2.7 and loss factor of 0.005. In general, the electrical properties are on par with glass ceramic.
Wiring capability of the packaging technology, in comparison with surface laminar circuit (SLC) and alumina/glass ceramic, is described in Table 1. Increasing wiring capability is indicated; peripheral C4 array is the least complex, moving up through 7 and 10 perimeter signal rows up to full area arrays. Single, double and triple dense refers to increasing C4 signal density for a given area. With current ground rules, the new packaging technology can wire out up to double-dense full area array footprints. This is surpassed only by alumina or glass ceramic, which can wire out triple-dense footprints with additional layers. All information described is for 225 micron C4 pitch. Extensions to C4 pitch below 212 micron, and other enhancements to further wireability, are in progress.
Materials: Because the silicon chip's mechanical and design characteristics are fixed, and the laminate was largely constrained by design considerations, engineers look to advanced materials to optimize reliability. Design elements were combined to further optimize the chip carrier system. One of the defining choices of the new packaging technology was to implement stress relief into the laminate itself, by choice of a compliant, flexible dielectric material. Just as solder columns provide stress relief to ceramic carriers, the laminate itself provides stress relief to its solder connections. This provides overall thinness, obviates the need for complex LGA hardware and contributes to good creep and shock resistance as the solder connections need not have a high standoff to have high reliability. The compliance of the laminate material cushions each BGA and spreads about the imposed stresses. The laminate dielectric absorbs a modest amount of internal shear strain under the die region, as well as from each solder ball connection. Patterns of strain in the various structural layers between the chip and printed wiring board, and elsewhere, are well-dispersed and controlled. In particular, the underfill is evenly stressed and concentrations are avoided. It was found that the thinness and flexibility of the laminate gives a thin-film characteristic to the package. There is an edge effect region surrounding the die that is not necessarily DNP-related. By designing copper circuitry and plated through-holes capable of withstanding this internal strain, the package essentially internalizes and solves a large portion of the overall chip-to-PWB CTE mismatch problem in a manner that is relatively transparent to the package user.
The ability of the laminate to provide stress relief to both the solder connections and the underfilled chip connections contributes to high reliability. The requirements of underfill adhesion strength, chip/lid adhesive strength, chip fracture strength and other critical interfaces are eased by the low-stress approach.
Another combination of design elements is the special treatment of the materials forming the central core of the stripline format. Serving as an electrically active ground plane, it also performs the function of reducing thermal expansion. While this layer is only 50 microns thick, the special low-CTE copper-invar-copper material provides sufficient stiffness so the laminate has a near-optimal CTE of 10 to 12 ppm/°C. Generally, having a lower CTE laminate can give a better match to the chip and thereby minimize warpage and internal strains. Having a higher CTE laminate can give a better match to the PWB and result in lower solder connection stresses. The laminate CTE was chosen in conjunction with the stress-relieving laminate material characteristics to optimize overall reliability scores.
 Figure 5. Cross-sectional view of an HPCC attached to a circuit card with 1-mm pitch BGA and external heat sink. |
With the low-stress laminate properties, it was possible to bond a thick copper lid to the chip with a robust, compliant thermal adhesive without creating excessive internal stresses. While restraining warpage through the use of a bonded lid can improve flatness and reduce stresses on a BGA, a lid necessarily adds internal stresses as the natural tendency of the chip and laminate to warp are restrained. A low-stress, CTE-controlled laminate offsets this behavior so effectively that the use of an unbonded grease-filled interface chip-to-lid is unnecessary. With its present design, an HPCC has a stable, reliable internal thermal resistance of about 0.32°C/W, for a 14.7-mm die/42.5-mm package. It can accommodate a large adhesive-bonded heat sink for a simple, high-performance thermal solution.
An essential activity of development was to define a tough, crack-resistant outer dielectric layer material that could withstand the strains imposed on it while retaining the compliant nature of the laminate. During development of the packaging technology, it was apparent that resin cracking of a trial soldermask material limited the reliability of the packaging system. Resin cracking manifests itself as a cohesive material fatigue fracture in the outer soldermask layer, primarily because of thermomechanical stresses between the soldermask material and copper circuitry. Cracks intitated and grew with temperature cycling. The fatigue life to cohesive failure could be further influenced by other elements that apply stress, such as solder connections, chip and underfill. Such cracks invited moisture-related insulation resistance losses and posed other problems. A search for a better soldermask material, which would not upset the desired overall behavior of the laminate, led to the choice of a fatigue-resistant material with a higher Tg and lower dielectric constant than the trial soldermask. The present HPCC includes this fatigue-resistant soldermask material and, with it, has virtually eliminated resin cracking. Estimates of cycles to fail by resin cracking, for 0/100°C accelerated thermal cycling (ATC) conditions, are in excess of 400,000 cycles, as opposed to 2,000 to 3,000 cycles realized with a trial material.
Packaging Reliability
The status of comprehensive reliability tests are shown in Table 2. The test vehicle included a 14.7-mm die, 42.5-mm laminate with 1-mm thick lid for module format tests and a 110-mil thick card with a 125 gram heat sink for card format tests. Module reballing and surface mount reuse are included, along with Joint Electronic Devices Engineering Council level-4 moisture preconditioning stress. Finite element models were extensively used to direct the choice of test vehicle sizes, choose risk sites to electrically monitor potential opens, identify worst-case usage/test conditions and are being further used to develop overall reliability models for the new packaging technology. The module package is able to withstand 1,750 cycles of 125/-40°C temperature cycling. In card-format temperature cycling, no evidence of BGA wearout exists in testing to date; therefore, the BGA life projection is approximate. Based on test results and models, prediction of BGA fatigue life, with a heat sink attached, is estimated at approximately 30,000+ cycles of life for typical 25 to 85°C Tj temperature daily usage cycles. Similarly, prediction of fatigue life of internal signal lines (related to internal strain of the laminate), with module on a card with a heat sink, is estimated to have a usage life of approximately 50,000 cycles. No other reliability wearout mechanisms have been identified for this technology; qualification testing will continue until all necessary test limits have been verified to meet design objectives. Future extensions to larger die and body sizes are planned.
AP
David Alcoe is a senior engineer scientist, Kim Blackwell is PBGA product manager, and ERIC LAINE is the worldwide organic packaging applications manager at IBM Microelectronics. For more information, contact Kim Blackwell, 1701 North Street, Bldg. 257-2, Endicott, NY 13760-5553; Fax: 607-757-1156; E-mail: [email protected].