Partners in Manufacturing: Increasing performance and speed with wafer bumping

Wafer-level processing provides effective solutions to demanding requirements.

By Jack Bogdanski, Dr. Paul A. Magill, Dr. Boyd Rogers and Robert Lanzone

There are a number of interrelated factors, involving both technology and economics, that can lead an electronics manufacturer to move from wire bonding to flip chip technology. One of the primary drivers is often the need to incorporate very high I/O requirements into a high-density, high-performance, ultra-fine pitch device. When such a situation arises, wafer-level processing can provide an effective solution. This process involves redistributing the I/Os from the perimeter to the interior of the component, followed by the creation of area array solder bumps for the flip chip application.

Figure 1. Integrated microprocessor and memory module. (Courtesy: White Electronic Designs.)
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An example of a successful wafer-level processing application incorporates a three-die, multi-chip package combining a processor and level two cache on a single interposer, for a high-reliability embedded control application (Figure 1). The device is designed to function in a particularly challenging environment, characterized by high temperature, high humidity and high acceleration. By interconnecting the three die on the interposer, the total I/O count of the module is reduced from 560 to 255.

Using wire-bonded components to build this interconnected device, even at the lower I/O count, could have presented a number of challenges. The module would have consumed a large amount of real estate on the printed circuit board and produced a high level of inductance. Due to the ultra-fine pitch of the wire bond pads, conventional flip chip attach processes could not be used. Therefore, the decision was made to use a wafer-level process to produce the high levels of density, performance and speed required by the design.

Wafer-level Processing for Flip Chip

The principal criteria for the redistribution and bumping included a well-qualified, industry-standard, reliable production process. High-lead solder was also required to provide the advantages of reduced electromigration and high flexibility. Accomplishing the desired result involved collaboration between the two parties – the device manufacturer and the wafer processor – to identify and implement the most effective method for the specific wafer being used, an industry-standard product initially designed for wire bonding.

Figure 2a. Resist template.
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The merchant bumping industry is today in its infancy, though customer demand is driving a rapid increase in production capacity. In many merchant operations, processing begins with transportation of the wafers from a wafer fabrication facility to the wafer bumping facility.

Figure 2b. Patterned metal.
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There are several options available, including redistribution in single or multiple layers or bumping over an existing bond pad location. In addition, the redistribution metal layers can be comprised of aluminum or copper. The material chosen is determined by the requirements of the substrate provider and the electrical requirements of the integrated circuit (IC) designer.

For the die bumped for this module, the process includes both redistribution in copper and an additional dielectric layer. First, a spin-on, photoimageable dielectric is applied to provide a non-conducting layer for electrical separation on top of the wafer. Second, a redistribution layer is applied to reroute the I/Os from the perimeter to the interior portion of the die, yet retain an electrical connection to the original contact pad. For this process, a lift-off metal technology is used. This is a two-step process for patterning metal layers on an IC.

Figure 3a. Via formed in BCB.
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In the first step (Figure 2a), a resist template is formed on the wafer, with openings where metal patterning is desired. In the second step, metal is evaporated through the resist stencil and the resist is dissolved or lifted off along with the unwanted metal. The results of this patterning are shown in Figure 2b.

A second polymer layer is then applied. Using an organic dielectric can provide a uniform, planar surface for the bumping process. For a contract-bumping manufacturer, removing topography issues from the manufacturing flow provides an enormous advantage. Benxocyclobutene (BCB) has a number of properties that make it suitable for a final level passivation, including low moisture uptake, a low dielectric constant and a high degree of planarization over topography that is usually found on ICs. One other consideration in forming the redistribution traces and new via openings is to reform the metal contact opening from a square to a circular opening.

Figure 3b. Via over redistribution metal.
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The next step in the process involves the creation of the solder interconnect structures over the metal contacts. This process for the creation of the solder bumps involves forming an under bump metallurgy (UBM) layer on the substrate, and then electroplating for selective deposition of solder on patterned areas of the UBM. Excess portions of the UBM are removed in a wet etching process after the solder bumps are formed.

The electroplating process eliminates the need for separate photolithography steps to pattern the solder structure and the UBM layer. As a result, the process requires fewer steps to define both the solder structure and the UBM. For this particular application, bumps of 125-µm diameter are created on a 250-µm pitch. Images of the solder bumps after plating and after reflow and UBM removal are shown in Figures 4a and 4b.

Test, Dicing and Assembly

Once the bumping process is complete, the wafers are transferred for completion of the process under the aegis of the manufacturer. A series of wafer sort tests, including die shear and bump shear, are conducted to ensure that yields meet specified requirements. Over the course of a year, it has been demonstrated that the bumping process has created no additional yield issues at the wafer level.

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With reliability confirmed, the wafers are diced and assembled into the modules. Of special importance for obtaining a high yielding assembly process is bump uniformity. Table 1 shows the bump uniformity for this process; the target height was 105 microns in this example.

Figure 4a. Patterned electroplated solder.
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As a result of bump and flip technology, individual components can be placed closer together than by using wire bonding. It reduces the total area consumed on the printed circuit board by more than half – from 1,330 mm2 to 525 mm2. At the same time, inductance is reduced significantly, from a high of 4.0 nanoHenries to 0.5 nanoHenries, enhancing the device's processor speed and performance.

Figure 4b. After reflow and UBM removal.
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With assembly complete, the part undergoes full burn-in and functional testing at extended temperatures. Current volumes for this particular application are expected to remain constant, with new designs for related products anticipated.

The potential for incorporating this type of bump and flip chip technology into high-volume applications also exists, and is projected to increase as advances in semiconductor fabrication process technology continue to minimize die size. The economic factors involved in expanding the use of flip chip technology are both application-dependent and volume-dependent.


In high-performance applications, wafer and die costs can represent approximately 60 percent of the total processing cost. Extending the technique to other applications, such as telecommunications and computer products, could result in overall process cost reductions.

To enhance the potential for cost reductions in higher-volume applications, a number of different wafer-level processes involving electroplating technology are available. Selecting the appropriate redistribution and bumping process is determined by each application's specific requirements for reliability and related performance factors.

JACK BOGDANSKI, director of marketing, can be contacted at White Electronic Design, 3601 E. University, Phoenix, AZ 85034; 602-437-1520; Fax: 602-437-9307; E-mail: [email protected]. PAUL A. MAGILL, Ph.D., chief technical officer, marketing, BOYD ROGERS, principal technologist, and ROBERT LANZONE, vice president of sales and marketing, can be contacted at Unitive Electronics Inc., P.O. Box 14584, Research Triangle Park, NC 27709-4584; 919-941-0606; Fax: 919-941-5097; E-mail: [email protected], [email protected] and [email protected].


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