By Daniel K. Ward
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In today's state-of-the-art designs, an interconnect war is being fought between the input/output (I/O) pitch of semiconductors and the substrates/ packages to which they are connected. Semiconductor features are being miniaturized at a faster rate than connecting substrates, which results in interconnect incompatibility between these two parts of the system. This incompatibility limits integrated circuit (IC) packaging types that can be used on a particular application, limits availability of compatible substrates, creates less-than-robust assembly processes that reduce yield and throughput, and increases overall system cost.
When integrated circuits were first introduced, they were not sophisticated silicon, but rather small circuits with transistors, resistors and capacitors. These circuits were mounted on daughter boards (ceramic or laminate) with terminals protruding from one edge (today we would call them multichip modules [MCMs] or single in-line packages [SIPs]). These terminals (leads) were placed into drilled holes in a motherboard and wave-soldered along with other through-hole components. Pads on printed wiring boards (PWBs) could be easily patterned and drilled to accommodate these parts because of their lead pitch similarity to most other leaded parts assembled at that time. The pitch war between components and PWBs had not yet begun, and there was peace in Assemblyville.
The first “all silicon” ICs were typically packaged in dual in-line packages (DIPs). The generally accepted body size was (and still is) 2.100 x 0.750 inches for the 40-pin DIP. This IC package has 20 leads per side bent at ~90 degree angles, which fit through-holes drilled and plated in a PWB. Lead pitch is typically on .100 inch centerlines, and PWB pad geometry, hole size, and “line and space” features had to be tightened along with increasing the number of board layers to route inputs and output from these parts. The PWB industry met these challenges, but had to make some major changes in PWB processing. The pitch war between the IC and the PWB had begun.
Next came surface mount technology (SMT). Leaded ICs packaged in early gullwing and J leaded plastic leaded chip carriers (PLCCs) both had sufficiently less lead compliance and solder interconnect joint strength than DIPs. Thus, they were made with the smallest possible body size to lessen the effect of stress caused by the coefficient of thermal expansion (CTE). As component lead count grew, lead pitch got smaller to keep the size/stress relationship under control. Eventually, lead pitch became as low as 0.3 mm, which required PWB lines and spaces as low as .006 inches. Routing layers and line and spaces issues became real problems. PWBs were becoming very difficult to produce at normal yields at the board shops. Inspection and yield costs were being passed to the assemblers. Many solder printing and component placement battles were being fought over the smaller and tighter features. The pitch war was heating up and the ICs were winning. Assemblyville was struggling to keep production output and yield at acceptable rates.
Then, when it looked like IC pitch was going to be limited by IC package body size and PWB yield and assembly issues, ball grid array (BGA) packages came on the scene. BGA area array leads with pitches of 1.0 to 1.2 mm could replace the unpopular 0.3 mm peripheral leaded parts. PWB's pitch capabilities would not be tested by BGAs. It began to look as if peace was coming to the pitch war. Pitch was no longer such a big deal.
However, peace was for but a brief time. Soon, flip chips and CSPs entered the battle. Both components are die-size or near die-size area array bumped devices, with extremely small pitches (0.20 to 0.25 mm). PWB manufacturers were again under the gun to produce products with extremely small and accurate features. Routing of the small devices also increased the layer count of the PWBs. Assemblyville had problems obtaining PWBs at any reasonable cost, and assembly quality problems were rampant. The pitch war had heated up again, and battles are still being fought in Assemblyville today.
What about the future? Is peace on the horizon? According to Semiconductor Industry Association roadmaps, lead count will continue to increase for individual ICs, and lead pitches will continue to become smaller. Can the PWB industry keep pace with flip chip and CSP components decreasing feature size? In my opinion, the answer is, absolutely no.
Let's explore the technical issues. Semiconductor features are measured in micrometers. A typical line and space on a mature semiconductor would be 1.00 micrometer. On a leading-edge semiconductor, this could be as low as 0.25 micrometer. In the PWB world, features are measured in decimal inches. Typical line and spaces would be 0.005 inches (125 micrometers) and leading edge would be 0.003 inches (75 micrometers). It is obvious with this large disparity in feature size that either costly silicon will continue to be added to ICs to make compatible interconnect sites (wire bond or flip chip) or that some type of interposer has to be developed to mate the line and space features. This is where the war is raging today. What technology can and will be developed?
One possible solution is that semiconductor manufacturers can make interposer packages of silicon (silicon-on- silicon 3-D assembly) that will be compatible with today's PWB features. A second possible solution is to manufacture PWBs like ICs with IC features. Either way, the pitch war will ultimately have a winner, and the spoils of victory and the agony of defeat are bound to irreversibly change life as we know it in Assemblyville.
DANIEL K. WARD is manager of advanced electronic packaging for Delphi Delco Electronics Systems, One Corporate Center, P.O. Box 9005, Mail Station: D-16, Kokomo, IN 46904-9005; 765-451-3093; Fax: 765-451-3115; E-mail: [email protected].