Teradyne Debuts VLSI Test System

SEMICON West '00—July 12, 2000—In San Jose, Cal., today, Teradyne Inc. introduced a VLSI test system that the company says will allow a full range of test capability without requiring hardware changes or system upgrades.

By Jason Rothman

SEMICON West ’00—July 14,2000—Semitool’s Paragon line of electrochemical deposition tools will include Royal Phillips Electronics new integrated metal-film metrology system, say the companies.

The collaboration arose to address the industry’s need for tools guaranteed to operate well together, eliminating one issue facing customers moving to 300mm. “Semitool has come up with a proprietary process to repair the seed layer before they put the ECD plating over it,” says Bill Gately, General Manager for Phillips Analytical in Boston. “In order to properly do that they need [metrology] within their tool to measure the seed layer when it comes into the tool so they know first whether it needs to be repaired and second how it needs to be repaired,” he says.

He added that Phillips already works with Novellus and Applied Materials and that Phillips suggested a stand-alone box to measure the wafers. Semitool suggested combining the two tools to simplify the process.

The new combined system first measures the seed layer of incoming wafers. It shoots a nanosecond laser pulse onto the wafer’s coating, creating an acoustic wave that moves across the wafer like throwing a stone into water, according to Dr. Tom Ryan, a Product Marketing Manager for Phillips. Then a probe laser measures the wave’s velocity. A computer then reads the information and a robot arm takes the wafer either to the ECD plating stage or it sends it back to repair the seed layer.

“We would like to become the standard metrology that can be utilized as a common link to all these processes,” Gately said. “We view this as a first step in a strategic direction we are heading in,” he says.


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