by Larry B. Levit, Tom M. Hanley, Frank Curran
The effects of electrostatic attraction and its role in contamination control will likely be a greater concern with 300 mm, even in ISO Class 3 (Class 1) cleanrooms; if this potential problem is not properly considered, a fab could experience a 20 percent increase in particles/wafer pass on all tools.
Semiconductor manufacturing faces increasing demands for contamination control. Even 50-nm particles can kill a die. Since there are many more such small particles in the environment than larger ones, the issue of contamination control becomes increasingly critical as device dimensions shrink.
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Theoretically, static electricity increases the number of particles landing on exposed surfaces, thus defeating much of contamination control protocol. We predict that the rate of electrostatic attraction (ESA) will be greater for 300-mm wafers than for smaller wafers. Our measurements show that, for 300-mm wafers, contamination from electrostatic attraction will be greatly increased with the current levels of static charge seen in present cleanrooms. ESA represents a contamination barrier that must be addressed by a rigorous static charge control program, as discussed in the Semi E78-0998 Electrostatic Compatibility Guide [1].
In cleanrooms, products and fixtures have little surface contamination and are subjected to a minimum of humidity and natural ions in the air. Consequently, the static charge developed by handling does not dissipate efficiently and grows to extraordinarily high levels. Since SiO2, a very good insulator, coats the underside of wafers, there is no way to dissipate the static charge via grounding. Teflon and quartz, commonly used in cleanrooms, are also extremely good insulators and thus hold static charge tenaciously.
 Figure 1. Charge distributions. The bottom represents a significantly greater contamination threat in a cleanroom. |
The electric field from charged wafers creates ESA of contaminants in the air, increasing the level of contamination over that of only particle sedimentation [2]. Since the electric fields from charged objects could defeat most existing contamination control programs, static control on insulators becomes a critical issue. The levels of static charge developed on reticles, pods, cassettes, and wafers are typically in excess of 10 kV (and often considerably higher).
It is rare for any object to sustain a voltage level of 1,000 V in a regular room, as humidity and surface contamination provide a discharge path.
A cleanroom uses constantly moving unidirectional airflow to keep airborne particles from settling on contamination-sensitive products. Particles are literally drawn out of the laminar airflow by the electric fields related to surface charge. Studies show that if wafers are charged to a potential of 4,000 V, the effects of static charge represent a substantially greater contamination source than that of sedimentation (settling of particles out of the laminar flow) [3]. Recent measurements of ESA and contamination control made on wafers in a semiconductor-manufacturing environment [4, 5] clearly show ESA as a major contamination mechanism.
Both the observations and the theoretical treatment show that ESA becomes greater for smaller particles. This is expected, as the aerodynamic forces decrease with smaller particle size, while the electrostatic forces on a particle of a given charge are unchanged. Thus, we set out to estimate the effects of wafer size on contaminating ESA.
Theoretical consideration [6]
Aerodynamic gravitational and electrostatic forces act on particles moving through the atmosphere of a cleanroom. The aerodynamic forces can be described in terms of viscous drag; electrostatic forces are described by Coulomb's Law. We assume the charge on a particle is zero on average, with statistical fluctuations characterized by a Boltzman distribution. This assumption yields the minimum force on particles, as compared with the case where the average charge on the particle is not zero. For example, Fig. 1 shows two distributions: one with an average charge of zero and the other offset by two electronic charges. The latter represents a significantly greater contamination threat due to ESA.
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Under the assumption of a particle distribution that is charge-neutral on average, the composite force on a particle due to aerodynamic, gravitational, and electrostatic forces was computed. The deposition velocity (Vd) determined from these calculations is loosely the speed at which the particles approach the wafer surface under the influence of these forces. A graph of deposition velocity vs. particle size (dp) shows that large particles are efficiently drawn to the surface by gravitational forces, but small particles are efficiently attracted electrostatically (Fig. 2). This theory has been tested, showing that the contribution from ESA in a Class 1 cleanroom was >400 percent of the sedimentation rate for 0.3-mm particles, where the wafer was at a potential of 2,000 V.
In the calculation cited above, the acceptable levels of electrostatic field were determined based on the value of the electric field at one wafer radius (Rwafer) above the wafer. Since electric field lines emerge perpendicular to the wafer's surface and remain parallel for a distance of ~Rwafer before they begin to diverge, the field is most intense and remains essentially constant out to this distance. At r >Rwafer the field drops off. At large distances, the wafer acts as a point charge and, thus, the field varies as 1/r2, where r is the radial distance from the point charge (Fig. 3).
Due to the shape of the field, the attractive force extends out farther for larger wafers. The volume over the wafer in which ESA happens is proportional to the cube of the wafer diameter. We carried out two sets of experiments to predict the relative effects of ESA on 300-mm wafers. The first involved adding ionization in the load-unload port of an epitaxial reactor and measuring the amount of particle contamination on a large number of wafers. The second experiment involved biasing wafers to ground potential and to 2,000 V, and leaving them in an ISO Class 3 (Class 1) minienvironment for five weeks. Both experiments were carried out with wafers of various sizes to study the fluctuations of ESA with wafer size.
Ionization experiment
We acquired surface scan particle count data for 14,000 wafers over an extended period of time with ionization present in the load-unload area of an epitaxial reactor. Ionization bars were installed to assure that the potential on the wafers was kept close to zero. Part of the data was acquired with the ionization bars turned on and the rest with the ionization bars turned off.
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RIGHT. Figure 5. Effects of wafer size on ESA measured as the rate of ESA compared to sedimentation. Data are from 16,338 wafers.
Figure 4 shows the ESA measurements for ~14,000, 150-mm wafers, where the distribution of particle sizes is plotted for particles as small as 0.15-mm. The blue bars represent the data collected with the ionization off and the black bars correspond to the data with the ionization turned on. The uncertainties are calculated as the standard deviation of the mean of the values.
The difference between the two data sets in Fig. 4 is rather dramatic: For the 0.16-mm bin, the difference has a standard deviation of 9.3 deviations of the mean. This corresponds to >99.9999999 percent confidence that the effect is real, confirming that there is significant electrostatic attraction.
To assess the effects of wafer size on ESA, we studied 100-mm and 150-mm wafers in exactly the same way as described above. We defined the parameter delta (D) as the fractional increase in particle count caused by ESA over sedimentation. For example, for 150-mm wafers, this parameter is
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Delta computes the fraction of particles resulting from ESA and should be the same if the ESA is the same for all wafer sizes. Figure 5 is a plot of D vs. particle size for scans over a total of ~16,000 wafers. The values of D are higher for 150-mm wafers than 100-mm wafers. Although it is difficult to extrapolate the data to 300-mm accurately, the difference between the ESA rate for 100-mm and 150-mm wafers is obvious. The magnitude of D depends on the speed of the airflow in the cleanroom and the distribution of particle sizes in the environment. While this will vary from location to location, the 45 percent ratio corresponds to a 31 percent increase in particles per wafer pass (PWP) caused by ESA. We expect the rate for 300-mm wafers to be even higher and thus, quite significant.
Biased wafer experiment
As a confirmation of the ESA vs. wafer size effect, we placed 100, 150, and 200-mm bare wafers in an ISO Class 3 (Class 1) minienvironment for five weeks. One of each size was placed on a grounded wire in the minienvironment and another on a wire biased to 2,000 V. During the exposure period, we counted the particle level within the minienvironment daily and found the number of particles consistent with an ISO Class 3 (Class 1) minienvironment at 0.5mm-particle size.
Initially, the wafers had <20 particles on them. Based on an initial data run, the number of particles on the cleanest wafer after the exposure was at least 1003 the initial particle level. After scanning the wafers and counting the particles, we found that the effects of ESA during this extended exposure were dramatic. Figure 6a and b shows scans of a grounded wafer and a 150-mm wafer biased to 2,000 V, respectively.
 Figure 7. The effects of ESA on 100-mm and 150-mm wafers. |
If the average particle size were greater in the ionization experiment, the effects of ESA would not be as great (see Fig. 2). The voltage on the wafers in the ionization experiment was likely lower than in the 2,000 V bias experiment. In fact, the effects were so immense that the surface-scanning particle counter overflowed. As a result, we could not extract the 200-mm wafer data and only the 1.00-1.47-mm particle sizes for the 100-mm and 150-mm wafers were counted.
 Figure 8. A 200-mm wafer biased to 2 kV after exposure in an ISO Class 3 (Class 1) minienvironment. |
Figure 7 shows particle count data and D. As mentioned above, the effects of ESA are more dramatic than for the ionization experiment. The effect shows >200 percent sedimentation contribution due to ESA. It also shows that the effect on 150-mm wafers is greater than the effect on 100-mm wafers. Visual inspection of the 200-mm wafers shows an even greater effect (Fig. 8).
We used the results of 100-mm and 150-mm wafers to extrapolate the rate of contamination to the 300-mm wafers. The conservative result comes from the data taken on a tool with essentially no static charge on the incoming wafers. We predicted that PWP in such a tool will increase by about 20 percent for 300-mm wafers, assuming a linear relationship between wafer size and D. In the more aggressive data acquired in an environment with 2,000 V of static charge, we predict a 300 percent increase in PWP for 300-mm wafers.
Conclusion
Our data shows that ESA is an important consideration in contamination control. Even in an ISO Class 3 (Class 1) environment, killer particles have not been eliminated, just kept to a small number. It is clear that the effects of ESA on 300-mm wafers will be significant. A 20 percent increase in PWP on all tools in the fab would have large consequences on the economics of semiconductor manufacturing. A 300 percent effect would be disastrous. We believe a comprehensive static control program will have a greater effect on contamination and yield issues in the future.
Acknowledgments
Teflon is a registered trademark of DuPont.
References
- Semi E78-0998, Electrostatic Compatibility Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment.
- R.P. Donavan, Particle Control for Semiconductor Manufacturing, New York: Marcel Decker Inc., 1990.
- M. Inoue et al., “Aerosol Deposition on Wafers,” IES Proceedings, 34th Annual Technical Meeting, p. 423, 1988.
- Frank Curran, MS thesis, “The Effects of Static Charge on Silicon Wafers in the Semiconductor Industry,” The Engineering Council of England, Nov. 1997.
- L.B. Levit et al., “Contamination Control in Semiconductor Manufacturing,” Proceedings of Semicon Taiwan, Taipei, Taiwan, p. 409, Sept. 1999
- This section is excerpted from a presentation by R.P. Donavan, Semi SMI Advisory, on Semi E78-0998, Electrostatic Compatibility Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment, at Semicon West, San Francisco, CA, July 1, 1999.
Larry B. Levit received his PhD in experimental high-energy physics from Case Western Reserve University. He is a member of the EOS/ESD Association, where he participates in several standards committees, and a senior member of the IEST, where he is vice chairman of the RP-22 committee working on electrostatic charge in controlled environments. Levit is director of technology development for Ion Systems, 1005 Parker St., Berkeley, CA 94710; ph 510/704-5419, fax 510/548-0417, e-mail [email protected].
Tom M. Hanley received his BSChemE and MSChemE from the University of Missouri. He has been granted two US patents for epi reactor design and has several proprietary processes. He is a member of AICHE and ECS. Hanley is a senior research engineer at MEMC Electronic Materials Inc.
Frank Curran received his MS from The Engineering Council of England. He works as a senior project engineer at Analog Devices Corp.
Understanding electrostatic effects is a challenge
The work by the authors aids in providing an understanding of the electrostatic mechanisms as they relate to scaling of wafer and device dimensions. There are numerous challenges present as semiconductor manufacturing migrates to 300-mm processing technology. One of the challenges is to understand the effects that electrostatics will have on particle deposition, and to implement a cost-effective and sustainable electrostatic control program that addresses known issues based on a data-driven approach.
The authors provide a basis for which further work in actual 300-mm processing environments can be undertaken.
Julian Montoya, electromagnetic compatibility program manager, Facility Technology Development, Intel Corp.