Package test
BY RANDY SCHMIDT
Generally speaking, test is the process of attempting to sort defective products from non-defective ones. The integrated circuit (IC) manufacturing process creates defects such as contamination. Metal shorts and other defects that may occur during the fabrication process are screened at the wafer sort stage, while defects, such as wire shorts, lifted balls and bridging that occurs during the assembly process, are screened at the final test stage. Desired yields from established assembly processes are typically greater than 99 percent; electrical fallout that can be attributed to assembly-related defects should run less than 0.5 percent.
 Figure 1. The ATE test head houses the pin electronics card (PEC), loadboard and contactor/socket. |
Automated test equipment (ATE) is docked to a handler that is designed to shuttle the packaged IC into the test site. The handler notifies the ATE to start the test, then the ATE notifies the handler which bin the device will be assigned to based on the results of the test.
Summary of Tests
DC testing typically includes tests for opens and shorts, leakage on input pins (IIH/IIL test) and tri-state pins (IOHZ/IOLZ test), output voltage levels (VOL/VOH test) and device standby current/active power dissipation (ICC/IDD test). Opens-and-shorts testing verifies that all bond wires are connected properly, and also checks signal continuity from the test head to the device under test (DUT). Functional tests are performed to verify operational characteristics and to ensure that the device is functioning according to the requirements of the specific device application. Analog testing checks analog modules for amplitude, frequency, phase and amplitude/phase modulation.
Test Equipment
Although test platforms or systems may vary greatly from one manufacturer to the next, there are five basic components in a test system: the mainframe, test head, docking/interface, handler and change kit. The ATE mainframe houses the tester and DUT power supplies, decodes system controller commands, keeps and sets system timing, handles signal processing and formatting, and performs precise DC measurements.
The ATE test head houses the pin electronics card (PEC), loadboard and contactor/socket. PECs combine voltage, current and timing commands into coherent DUT input/output (I/O), while the loadboard is used to interface the device to the PEC. The contactor/socket is mounted to the loadboard and is used to contact the DUT to the loadboard. In some systems, the test head houses all of the functionality of the mainframe (Figure 1).
 Figure 2. Various package/wafer-handling systems interface with many different test heads. |
The docking/interface manipulates the test head to dock with the prober or handler, while the handler shuttles the DUT from the input section to the contactor/socket, then to the designated bin (Figure 2). Finally, the change kit is used to adapt the handler to specific package outlines.
Package Handling
High-volume production testing is automated with a mechanical device handler. These handlers are designed to handle specific package types, such as plastic leaded chip carriers (PLCCs) or quad flat packs (QFPs). A handler change kit is required for each package size or configuration (change in body size, thickness or lead configuration). A socket or docking plate may be required for the same package type if using a different socket or contactor. Handlers are broken down into two categories: pick-and-place handlers and gravity-fed handlers.
A pick-and-place handler is used for testing QFP/ball grid array (BGA) devices. These devices are not designed to collide with each other without causing damage to the leads and are handled in either a tray or tape-and-reel. Index times are usually longer compared to gravity-fed handlers.
A gravity-fed handler is used for testing PLCCs, small-outline integrated circuits (SOICs), shrink small-outline packages (SSOPs), thin SSOPs and plastic dual in-line packages. These devices are designed to be handled in tubes without causing damage. Index times are usually shorter compared to pick-and-place handlers.
Providing a Test Solution/Evolution
In the past, vertical integration of manufacturing activities encompassed the entire manufacturing process – from foundry to assembly and test. Along the way, because of cycle time demands, capacity and financial constraints, and the changing nature of the semiconductor industry, the subcontractor (subcon) community was born and semiconductor companies began to outsource portions of their manufacturing operations.
The semiconductor industry has continued to evolve with the continued growth of the “fabless company” model and the introduction of intellectual property (IP) providers and design service companies. More companies today are specializing and focusing on the design concept of the product and relying on the subcon community to provide the manufacturing resources.
To meet the high demands for short cycle times and low production costs, the assembly and test process must occur under one roof. The driving force in selecting an assembly and test solution will change as well. In the past, assembly was the driving force in the selection of a subcontractor; however, a shift is occurring in which a test solution is also factored into the equation. Manufacturers looking to outsource are concerned with all of the technical capabilities for both assembly and test; however, as the complexity of the devices increases, customers also will focus on test-at-speed issues, high pin-count test capabilities, mixed-signal test, large embedded memory test, testing system-on-a-chip devices, and the capabilities of sustaining test engineers to support these devices for the duration of a component's lifetime (Figure 3).
Test Considerations
Increased package density, increased device performance and the proliferation of package outlines also have challenged the subcontractor to develop custom handler and socket solutions that are inexpensive, yet robust enough to support a variety of manufacturing volumes.
Advanced digital blocks with high data rates and increasing I/O pin counts, complex analog blocks, large embedded memory arrays and the addition of radio frequency blocks on a single device will add to the challenge of providing cost-effective test solutions, especially when state-of-the-art ATE systems and instrumentation required to test these devices are themselves costly.
These technical challenges require that a test development engineer formulate a clear multi-site test strategy and a set of test methodologies to provide solutions to the test requirements. In the integrated device manufacturer (IDM) environment, this challenge is product-centric. In other words, an IDM test engineer typically is responsible for a particular mixed-signal device product family. The multi-site test solution and methodology is formulated around the product: ATE systems with resources selected to accommodate the product family, test methodologies for select device parameters within that product family and hardware solutions that are applicable across the entire product family.
 Figure 3. A test subcontractor needs to house a variety of test platforms and handling equipment to accommodate customer needs. |
In the test subcontract environment, however, the multi-site test methodologies and multi-site test strategies cannot be product-centric – they are test-centric. A test subcontract development engineer must formulate the multi-site test solutions based not on a specific mixed-signal device family, but on the ATE systems within the environment. Unlike the IDM model, where the ATE system is configured around a specific mixed-signal product family, the test subcontract ATE is configured to accommodate a broad range of devices and different customer test requirements. The test subcontractor is at the disadvantage of not knowing a particular IDM's product roadmap, product family variation and in-depth knowledge of a specific product device. A test subcontractor must use the same ATE system for a variety of semiconductor customers with devices targeted for different market segments. This necessitates that, for a test subcontractor, an ATE system configuration be broad-based with multiple options and system resources.
For a test subcontractor, the pressure to meet the customer's expected lower test cost places an emphasis on developing creative test methodologies that satisfy the test requirements on lower-cost test systems. This may mean testing mixed-signal devices on digital ATE systems or lower-end mixed-signal ATE testers. For example, the testing of a mixed-signal device that contains low-end performance analog-to-digital converters (ADCs) and is price-sensitive may not make it economical to test on a standard mixed-signal ATE platform. Typically, a digital ATE platform is lower in cost than a mixed-signal ATE platform with equivalent or greater digital test resources. The test requirements for the low-performance ADCs may specify testing for static linearity (INL, DNL), gain error, offset voltage and offset error. In this case, a novel test methodology is formulated by the test-centric test subcontractor to satisfy the customer's requirements on a digital ATE tester while meeting price demands.
Another example of achieving low test costs while also satisfying test requirements is phase-lock-loop (PLL) testing. Depending on the test specification limits and resolutions, it is possible to test for frequency stability, long-term jitter and frequency output without using analog instrumentation. It may also be possible to use active components on the loadboards (test interface hardware) to provide a low-cost test solution.
These examples illustrate the critical value of test methodologies that are employed from a test-centric view to meet customers' expectations. It also illustrates how a test subcontractor is continually challenged to achieve lower test costs, and how innovative test methodologies can achieve this goal.
Test subcontractors are now expected to work with customers at an even earlier stage of the device life cycle. The test subcontractor is becoming more of an extension of the customer's own manufacturing arm. As an extension, customers are relying upon the test subcontractor to assist in defining test strategies and appropriate test platforms. Test program development and test engineering activity are now required of a test subcontractor. In developing the test programs, a test subcontractor must now possess an ever greater technical and engineering experience level.
Acknowledgement
The author would like to thank John Ritchie of ST Assembly Test Services (STATS) for the research and insight he provided to support this work.
RANDY SCHMIDT, product marketing manager, can be contacted at ST Assembly Test Services (STATS), 1450 McCandless Drive, Milpitas, CA 95035; 408-858-1767; Fax: 408-941-1501; [email protected].