Ziptronix, Inc. finds funding for new wafer bonding process

Research Triangle Park, North Carolina–Oct. 30, 2000–Ziptronix, Inc., a spin-off company of Research Triangle Institute (RTI), has raised $6.5 million in its first round of venture capital financing to launch a new technology that integrates semiconductors of many types, materials, and functions within existing semiconductor wafer fabrication processes. Alliance Technology Ventures, of Atlanta, Georgia, is the lead investor.

“We offer the electronics industry the ability to integrate multiple semiconductor wafers without individually packaging the chips first,” says Ziptronix CEO Bill Clark.

Two proprietary Ziptronix technologies–room temperature wafer bonding and backside processing–form the basis for the process. The technologies, invented by RTI researchers, and the associated patents and applications have been assigned to Ziptronix by RTI.

“The Ziptronix process starts with a ‘host wafer’ containing many chips,” explains Paul Enquist, vice president of Research and Development. “Then, other wafers or individual chips are bonded to the host at room temperature. The substrate from the second wafer or individual chips is removed, leaving only a few microns containing the active electronics. Electrical interconnects are then made between the host and the bonded wafer or die using a standard via-based interconnect process identical to that used in semiconductor fabrication facilities to electrically interconnect different layers of a single wafer. The process can be repeated multiple times. The end result is an integration of what is currently many chips into a single chip.”

The company plans to license the technology to large semiconductor firms to produce integrated parts for electronic firms, and eventually produce standard parts using Ziptronix technology.


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