IBM, Infineon, and UMC building chips with 0.13-micron technology

East Fishkill, New York–IBM, Infineon, and UMC recently announced that they have begun building chips with the most advanced 0.13-micron foundry process technology currently available.

The announcement comes just 10 months after the companies first announced joint development of the 0.13-micron foundry technology. Customers are currently designing chips based on the process, and a variety of logic and mixed-signal chips are in initial production at IBM facilities in the U.S., Infineon production lines in Europe, and UMC manufacturing lines in Taiwan. First customer shipments of high performance chips for network communications and computing applications are expected early in 2001.

The 0.13-micron chip-making technology continues the semiconductor industry trend toward smaller, faster, more highly-integrated chip designs. The 0.13-micron process being used at IBM, Infineon, and UMC features a combination of true low-k dielectric insulation and the highest number of copper wiring layers–designed to meet the high performance and low power consumption demands of advanced customer chip designs. The true low-k dielectric insulation helps electronic signals move faster, according to the companies, potentially adding up to a 30% boost in computing speed and performance.

“This significant manufacturing milestone is a result of our commitment to rapidly develop and implement a production-ready 0.13-micron foundry technology faster than our competition,” says Bijan Davari, IBM Fellow and vice president of technology and emerging products for the IBM Microelectronics Division. “This is a new development model for the industry. By cooperating on the development of the base technology, each of us can concentrate on our unique chip design and manufacturing capabilities to differentiate our offerings in the marketplace.”

By working together, IBM, Infineon, and UMC have established a common, baseline technology, offering customers multiple sources of supply for their components. Each company has the right to implement the technology in its own facilities.

“The jointly-developed technology covers a wide range of features including low power, high speed and mixed signal and RF devices essential for the implementation of Infineon’s next generation communication products and includes a high performance embedded DRAM option, enabling next-generation system on a chip applications,” says Dr. Franz Neppl, senior vice president of Infineon’s Corporate Development Division. “The collaboration is another successful step in Infineon’s strategy to share risk and cost for the development of very advanced technology processes.”

IBM, Infineon, and UMC are working to speed the delivery of products to their customers through various initiatives, including multi-project test wafers. For example, UMC has established a Silicon Shuttle program to allow customers to split the mask costs for this technology, helping them minimize cost and risk as they verify their advanced designs, IP, and prototypes in 0.13-micron silicon. This program is expected to greatly accelerate the adoption of this process as the preferred 0.13-micron technology for advanced ICs.

“We are already seeing tremendous interest in the jointly developed technology that UMC is marketing under the WorldLogicSM banner. UMC has already taped-out Silicon Shuttle test wafers carrying the designs of five customers. We have more than 16 additional foundry customers who have started their designs for this technology and will start initial production in Q1 and Q2 of next year,” says Dr. Fu Tai Liou, senior vice president and chief technology officer of UMC. “With both IBM and Infineon reporting similar customer interest, it is clear that this technology is rapidly gaining acceptance as the premier global foundry solution for the implementation of advanced integrated circuits.”

The three companies’ joint development work has been conducted at the IBM Semiconductor Research and Development Center (SRDC) at IBM?s East Fishkill, NY facility. Follow-on work includes plans for further development of a 0.10-micron process technology.


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