Santa Clara, California–Sequence Design Inc. is collaborating with the Semiconductor Technology Academic Research Center of Japan (STARC) to produce highly accurate interconnect models for a standardized 130-nanometer (0.13-micron) silicon process.

STARC is an organization funded by Japan’s leading semiconductor manufacturers with the goal of strengthening the country’s technological foundation in silicon semiconductors as well as enhancing international competitiveness. STARC member companies include Fujitsu, Hitachi, Matsushita, Mitsubishi, NEC, OKI, Rohm, Sanyo, Sharp, Sony, and Toshiba.

The aim of the STARC project is to create a common 130-nm design rule specification for use by third party library and IP vendors in the creation of a single set of libraries or IP blocks that customers may use no matter which member foundry is targeted. This common design rule specification also will enable the major Japanese foundries to build standardized IP to share.

“As process technology advances, achieving the most accurate interconnect models is essential to being able to predict parasitic effects on timing of real silicon,” says Koichi Fujita, general manager of Advanced CMOS Technology at Fujitsu Limited and member of STARC. “I am confident that our efforts with STARC will help to identify the key technologies we need to be successful at 130-nm and beyond and benefit our customers greatly.”

“STARC and its member companies continues to work with leading edge companies like Sequence Design to implement ‘best-in-class’ technologies such as Columbus because of its highly accurate interconnect modeling capabilities,” explains Tom Nukiyama, executive technical director of NEC Electronics, Inc. and member of STARC. “Sequence’s interconnect modeling technology has shown impressive capabilities and we are confident that its use will ensure generation of highly accurate interconnect models for this advance in 130-nm silicon process technology and beyond.”

“We are very pleased by STARC’s recognition of our Columbus technology. It is yet another validation of the importance of accurate interconnect modeling for 180-nm and beyond,” says Vic Kulkarni, chief operating officer for Sequence. “In working with some of the world’s leading traditional and pure foundries on the latest silicon technologies, detailed modeling capabilities are essential to maintain accuracy. Columbus is the most accurate interconnect modeling tool for today’s advanced processes–which is essential in order to predict real timing performance in silicon.”