Santa Clara, California–Sequence Design, Inc., a specialist in timing and power optimization solutions for system-on-chip (SOC) design, has received U.S. Patent No. 6,151,568 to protect its technology for the analysis and optimization of power behavior in very large SOC integrated circuits (ICs).

“This patent forms the basis for an entire category of SOC design automation,” says Vic Kulkarni, chief operating officer of Sequence. “It describes the only practical method currently known to implement pre-synthesis, full-chip power analysis and optimization for architectural design closure. As chip sizes continue to increase, and as full RTL to GDS II physical design strategies become prevalent, the significance of this basic work will grow and grow.”

The Sequence patent, authored by Dave Allen, Lorne Cooper, Jerry Frenkil, and Tom Miller, makes possible an accurate, full-chip RTL power analysis without requiring the design to be synthesized to gates. Under its methodology, a step called “inferencing” is first used to identify which parts of the chip microarchitecture will later be mapped into one of five specific circuit types: datapath, control logic, memory, I/O, and clocks. Advanced algorithms are then used to model how the different circuit types will dissipate power under given switching activities and in target silicon technologies. The result, claims Sequence, is an accurate power map of the chip that can be run on entire SOC ICs, execute one to two orders of magnitude faster than gate-level methods, and does not require the traditional intermediate step of logic synthesis.