Fremont, California–Avant! Corp. today unveiled details of its high-capacity, high-throughput inductance analysis solution capable of handling 25 million gate system-on-chip (SOC) designs.
“It is extremely difficult for a conventional RC extractor to model parasitic inductance effects in large SOC designs, because the whole physical layout needs to be considered,” explains Michael Jackson, deputy engineering head of Avant!’s ICDA subsidiary. “Star-RCXT can do extremely fast processing of large designs while using only a small amount of memory.”
As chip geometries shrink and operating speeds increase, the physical effects of parasitic capacitance, resistance, and inductance become increasingly significant. “Inductance, for example, can affect the timing as much as 30% for designs operating above 500 MHz,” Jackson says. “Avant!’s integrated approach to inductance analysis enables designers to accurately model all the parasitic effects–resistance, capacitance, and inductance–of large-SOC designs.”
Within its Milkyway-based SinglePass design methodology, Avant! offers Star-RCXT, a parasitic extraction tool, as well as StarSim-XT, which provides high-speed circuit simulation for designs with as many as 100 million transistors.
Star-RCXT and StarSim-XT use third-generation, network-reduction algorithms to obtain fast, accurate results that take into account all parasitic values, according to the company.