Motorola innovates packaging with new strategies

By Kathleen Peterson

Motorola Semiconductor Products Sector (SPS) is the strong, silent type. The industry might characterize the company as having been elusive in terms of its packaging developments in recent years, but behind this silence comes some good news for the packaging arena. Motorola SPS has been underground (quite literally), working on a number of cutting-edge products and technologies intended to drive the industry.

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The BAT-1 (bump-assembly-test) facility is Motorola's packaging claim to fame, which was clear in a recent tour – a first for any member of the trade press. Underground in Austin, Texas, this QS9000-certified 120,000-square-foot cleanroom, headed up by operations manager Gerry Hepburn, provides final manufacturing capabilities for both Motorola products and external companies. In 1994, BAT-1 began production of C4 evaporative wafer bumping and ceramic ball grid array (CBGA) packages. However, as the industry changes, so does the paradigm in which companies operate, and Motorola SPS is no different. In that vein, BAT-1 has recently refocused much of its research and development on plastic packages, and the interest in electroplated bump technology is spilling over from Motorola's Chandler, Ariz., facility and into BAT-1.

Currently, the evolution from ceramic to organic packages is garnering a good level of interest and profit for Motorola SPS. Its flip chip plastic ball grid array (FC-PBGA) was introduced in 1999 and, with a production capacity increase of five-fold, has been growing steadily since. With three package offerings in 1999, four in 2000 and at least six projected for 2001, FC-PBGA production is the thrust of BAT-1's assembly operations.

According to Andrew Mawer, senior principal staff scientist at Motorola's Final Manufacturing Technology Center (FMTC), flip chip packaging's advantages over wirebonding include greater die-to-substrate interconnect density, increased switching speed, a smaller footprint and more efficient power distribution to the integrated circuit (IC). The absence of wire bonds on the perimeter of the IC with FC-PBGA allows for minimum package-to-die size ratios, and several of these products incorporate Motorola's copper inter-connect fab process technology. Additional FC-PBGA benefits include good board-mounted solder-joint reliability, potential materials cost savings and a simplified package assembly process (when compared to ceramic BGA).

“The advantages of BGA have been well-documented since Motorola introduced the industry's first commercially available wire-bond-based PBGAs in 1993,” said Changhae Park, director of Motorola's FMTC. “Extending the PBGA to flip-chip complements advanced CMOS copper process technology and circuit designs, and delivers a comprehensive best-in-class solution to our networking, communications and computing customers.”

The package's laminate substrate is based on fine line and space high-density interconnect technology, which employs either laser or photodefined vias (depending on the product). Solder ball pitches currently range from 0.80 to 1.27 mm with future implementation of 0.65 and 0.50-mm pitch. The minimum bump pitch currently in production is 225 microns, while 150-micron pitch FC-PBGA feasibility has been demonstrated for future products. Bumping and assembly process development is being carried out at 100-micron bump pitch.

The future of FC-PBGA includes qualification to high-temperature reflow for lead-free assembly, maximum pin counts and GHz frequency capability, as well as low-profile cost-performance packages for portable applications.

Organic packaging is only half of the Motorola SPS story, however. The movement from evaporative bump processes to electroplating eutectic DCA changes the face of semiconductor packaging – at Motorola and industry-wide. According to John Franka, flip chip packaging technology manager at the Austin-based FMTC, “We believe electroplate is the wave of the future.”

That has been Motorola's strategy since 1997. At that time, Motorola's Chandler, Ariz.-based Strategic Manufacturing Deployment factory established an electroplate line, which is currently producing 4-mil bumps on 8-mil pitch for eutectic DCA applications. For both CBGA and PBGA, Motorola has demonstrated electroplate bump on aluminum and pure copper bond pads, and has established high-lead, low-alpha solder capability.

Motorola SPS has udertaken plans to launch an electroplate line at BAT-1 and will continue grappling with the sometimes tricky but crucial questions of “Should wafers be bumped, then thinned, or thinned and then bumped?” and “How soon should we provide eutectic and no-lead solder for components, and move from 150-mm pitch down to 100 mm?”

Asking the right questions at the right time is the key to any company's continuous success. It will be interesting to see how Motorola handles these challeges in the future.

Galileo Technology and IBM form networking technology relationship

SAN JOSE, CALIF. AND EAST FISHKILL, N.Y. – Galileo Technology and IBM have announced a communications technology initiative that is expected to enable network equipment manufacturers to design and implement high-performance and flexible next-generation Internet equipment.

This effort is intended to speed the development and introduction of networking products targeting high-growth applications, such as converged voice/data/video campuses, business-to-business service providers, and high-performance carrier-class and opticalnetworking systems, by allowing for interoperability between IBM's PowerNP network processor and Galileo's switching products.

Under the initiative, IBM intends to enhance its PowerNP architecture to seamlessly work with Galileo's next-generation switching products. Used in conjunction with Galileo's full-wire speed scalable switching, routing and Availability-of-Service networking products, customers using IBM's PowerNP are expected to achieve greater high-layer flexibility and deep-packet processing performance at OC-192 and 10 Gbps (gigabit per second) speeds.

IBM also plans to manufacture portions of Galileo's next-generation switching family using IBM's SA-27E ASIC process technology. IBM would manufacture these chips at its Burlington, Vt., facility in 2001.

“With its high-performance GalNet switching products, Galileo is expected to be an important contributor on the growing list of leading third-party hardware and software vendors who are committed to establishing common technology interfaces between all network chips,” said James Northington, vice president of network processing for IBM. “We believe the versatility of our PowerNP network processors can help revolutionize the communications industry, but we realize no company can single-handedly bring about that change. So we're working with companies like Galileo to create solutions that meet our customers' next-generation networking requirements.”

Photon Dynamics to acquire Image Processing Systems Inc.

SAN JOSE, CALIF. – Photon Dynamics Inc., the parent company of CR Technology Inc., has signed a definitive agreement to acquire Image Processing Systems Inc. (IPS) in exchange for approximately 1.3 million shares of newly issued Photon Dynamics common stock.

Based in Markham, Ontario, Canada, IPS is a leading global developer of eVision (electronic vision) technology for the display industry and other industrial markets.

The acquisition will expand Photon Dynamics' product offerings in the display industry and allow the company to leverage IPS's technology/skills in additional FPD applications and other industrial markets. The transaction is subject to the approval of shareholders of IPS, as well as court and regulatory approvals. The transaction is also conditional on satisfying pooling of interests accounting requirements.

The transaction is also expected to be accretive in Photon Dynamics' fiscal year ending September 30, 2001. From its headquarters in Markham, Ontario, Canada, and under the continued guidance of Ken Wawrew as president, IPS will operate as a wholly owned subsidiary of Photon Dynamics.

Hyundai licenses FormFactor's WLP process

LIVERMORE, CALIF. AND Taipei, TAIWAN – FormFactor Inc., a leading provider of complete wafer-level semiconductor test and packaging solutions, has licensed its wafer-level packaging and test processes to Korea's leading memory semiconductor manufacturer, Hyundai Electronics Industries Co. Ltd., for use in Hyundai's advanced DRAM devices. FormFactor's technology will enable Hyundai to lower back-end production costs for its DRAM products.

“FormFactor has developed the industry's first integrated process for wafer-level packaging and whole-wafer test. Both are crucial to continuous cost reduction in DRAM manufacturing,” said Farhad Tabrizi, vice president of strategic marketing and product planning at Hyundai. “By using FormFactor's MicroSpring contact-based wafer-level packaging and testing technology, we can significantly reduce our costs and enhance DRAM yields, while simul-taneously improving reliability of assembled memory modules.

FormFactor's patented wafer-level packaging technology fabricates the MicroSpring contacts directly on DRAM wafers. Then the wafers are either tested at the whole-wafer level or in singulated CSP form. The tested die are then assembled into memory modules by reusing the same contact acting as the chip-to-board interconnect.

Dan Hutcheson, president of VLSI Research, said, “Wafer-level processing in back-end packaging and testing of semiconductor chips has been a key industry goal for decades because it promises a step function reduction in cost, with additional cost reductions over time. Until now, wafer-level packaging with whole-wafer test technology has

not met chipmakers' requirements. FormFactor enables an integrated solution that delivers significant cost reduction as well as enhanced electrical performance and improved reliability.”

In related news, Teradyne Inc. has entered into a contract with FormFactor to develop a 128-device-under-test (DUT) DRAM probe card.

According to industry analysts, DRAM price per megabit has his torically declined at a rate of 25 percent per year, while total DRAM bits shipped have increased an average of 60 percent per year. This constant price erosion forces DRAM producers to reduce costs across the DRAM process, including probe test. In the past, the DRAM industry has found that the most effective method of reducing probe costs is to increase the parallelism of each touch and test of a wafer. Economic models used by Teradyne and FormFactor show that increasing from 32-DUT in parallel to 128-DUT in parallel testing can reduce the total probe test capital budget for a new 30,000 wafer-start-per-month 200-mm wafer fab by $50 million or more.

The 128-DUT probe card from FormFactor will be an extension of the MicroSpring contact 32-DUT and 64-DUT probing technology. To enable four-touch testing of 200-mm wafers, the probe card will have an active probing area slightly larger than 100 x 100 mm. FormFactor plans to ramp production capacity for the 128-DUT technology by mid-2001. The joint probe card development project will include releasing an approved specification for the 128-DUT tech nology, building samples, and testing the samples at Teradyne and jointly with customers. FormFactor and Teradyne will also work with other partners in the probe process, including prober vendors and probe card metrology tool suppliers, to ensure the availability of the infrastructure required to support the new technology.

Semi IP market to skyrocket by 2004

SAN JOSE, CALIF. – The worldwide semiconductor intellectual property (IP) market is forecast to grow from $442 million in 1999 to $2.94 billion in 2004, according to projections made by Dataquest Inc.

“IP is a key enabler of design reuse and is the only effective way of closing the 'design gap.' Without this technology, semiconductor vendors and OEMs will not be able to take advantage of today's semiconductor manufacturing advances,” said Jim Tully of Dataquest. “Although the IP market is very new, it is now hard to imagine the semiconductor industry without ARM, MIPS, Rambus and some of the other prominent IP players.”

A semiconductor IP block is a predesigned function to be implemented in a semiconductor device. These functions include physical library functions (analog or digital), basic blocks (such as counters and muxes) and system-level macros (cores or virtual components), including memory blocks. The microprocessor and bus interface blocks are expected to become the dominant features of the market by 2004.

“IP usage is driven by user demand and by the availability of suitable products from credible vendors. Today, most IP vendors are very small and are perceived by large potential customers as vulnerable,” said Tully. “Customers are reluctant to purchase strategically important IP from these companies until they are a little bigger and more stable. We believe the industry will pass through this stage within two years to emerge ready for stronger growth beyond 2004.”

Many IP vendors are entering and leaving the business. Dataquest analysts have observed that many of the entrants are design houses that are looking to capitalize on internal IP and steer the business into a more scalable model. “However, we believe that many of these companies will exit the market as they find the IP business to be very different to design services and beyond their current capabilities,” said Tully.

NEMI premieres new IPC standards

HERNDON, VA. – The National Electronics Manufacturing Initiative (NEMI) has recently premiered the first of the product data exchange (PDX) suite of standards developed by its Virtual Factory Information Interchange Project (VFIIP). PDX will be formally standardized through IPC as the IPC 2570 series of standards for supply chain communication.

The VFIIP-developed standards collectively form the beginning of a tool to facilitate the exchange of technical data among OEMs, EMS providers and their suppliers. The goal is to shorten the time and reduce the cost required to establish and maintain information-exchange partnerships across the manufacturing supply web.

The PDX standard, which includes all of the IPC 257x sectional standards, defines an XML encoding scheme for the product design and manufacturing information that feeds the electronics manufacturing supply chain. It will enable efficiency improvements by allowing partners to exchange product content, changes and subsequent manufacturing information in a common language. The initial standards are: 2571, Generic Requirements for Supply Chain Communication; 2576, Requirements for Supply Chain Communication of As-built Product Data; and 2578, Requirements for Product Design Configuration.

Through the IPC and, eventually, the International Electrotechnical Commission (IEC), these standards will be adopted nationally and internationally.

Call for papers

SAN JOSE, CALIF. – SEMI, in collaboration with International SEMATECH, is soliciting original papers for the SEMICON Southwest 2001 Critical Technologies Conference and Exhibits, which will be held October 15-17, 2001, in Austin, Texas. The conference will focus on wafer processing issues that are critical to connecting the technical requirements of the roadmap to the realities of manufacturing. Gate stack engineering reviews the processes, materials and equipment needed to solve the problems posed by reduced feature size and the resultant effect on device performance.

Papers will be selected from the following areas of interest:

Equipment and Process-related
Tool Issues
Chemical vapor deposition
Atomic layer deposition
Molecular beam epitaxy deposition
Misted vapor deposition
Chemical and Precursor Issues
Carbon-based precursors
Non-carbon-based precursors
Innovative chemical opportunities
Plasma etch formulations
Wet chemical etch formulations
Delivery systems
EHS Issues
Device Performance
CV analysis for equivalent oxide characterization
Gated diode structures
Transistor characteristics
Transistor reliability
Materials Characterization Issues
TEM characterization
XPS characterization
Grazing X-ray diffraction analysis
Chemical etch analysis
Process Integration of High-K Materials
Conventional and replacement gate flows
Thermal stability of high-k gate dielectrics
Back-end-of-line issues
Contamination concerns
Gate electrode materials

Abstracts are due January 31, 2001. Abstracts should describe the nature, scope, content, organization, key points and significance of the proposed presentation and include the author's complete contact information.

Submit materials to SEMI, Lurdes Rivera-Murphy, 3081 Zanker Road, San Jose, CA 95134; 408-943-7053; Fax: 408-943-7913; E-mail: [email protected].


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