Singapore–ST Assembly Test Services (STATS), an independent semiconductor testing and advanced packaging service provider, has introduced another IC package for the wired and wireless communications markets. Known as the Stacked Die Ball Grid Array (SDBGA), it is distinguished by its stacking feature, combining various ICs in one package, which can significantly reduce manufacturing costs, testing time, and real estate on the motherboard.
Both the mounting area and chip weight of an SDBGA can be reduced as much as 70%, compared to conventional packages. “The SDBGA’s multi-die application easily meets current market demand for communications devices. Increasingly, these devices pack a lot of capability into a smaller size, cost less, are easier to produce and offer faster time to market than a single chip solution,” says B J Han, STATS chief technology officer.
SDBGA has all the characteristics of near Chip Scale Packages (CSP)–advanced packages which are lighter weight, smaller size, and provide higher performance. It is the latest addition to STATS’ CSP family following the introduction of the Flip Chip Small-Thin Plastic BGA (FCstPBGA) last August.
With its two-in-one feature, the total SDBGA package height is typically 1.4mm. Popular SDBGA sizes are 8x8mm to 14x14mm and pin count between 80 to140.