Cadence unveils integration ensemble

February 26, 2001–San Jose, California–Cadence Design Systems, Inc. today introduced the Cadence Integration Ensemble hierarchical IC implementation tool for designing complex systems-on-chips (SOCs). IE is the next generation of Cadence’s synthesis/place-and-route (SP&R) solutions.

IE represents the industry’s next-generation SP&R solution that runs from register transfer level (RTL) to GDSII on a single database with single synthesis, placement, timing, and routing engines. The tool was developed in collaboration with a number of customers to handle designs of more than 25 million gates and process geometries of 0.12 micron and below.

There are many innovations in IE, including its being the industry’s first and only fully integrated, hierarchical, timing driven SOC design system. IE’s timing abstraction capabilities speed synthesis, timing, and design closure. IE includes third generation dynamic floorplanning functions that help to produce optimal floorplans. The IE system is built on a new, ultra-high capacity and high-performance SOC database, capable of handling designs of more than 25 million gates extremely effectively. The database provides a common platform for unparalleled integration of synthesis, placement, routing, timing analysis, power analysis, and signal integrity analysis.

“At STMicroelectronics, we have ever increasing need for timing predictability, capacity, and performance from EDA tools for our multimillion gate mixed analog-digital SOC class designs,” says Philippe Magarshack, vice president, Central R&D Group, Design Automation, STMicroelectronics. “We have worked very closely for the past year and a half with Cadence to address this requirement. As a result of our co-development work using IE, we have built a more predictable and reliable IC design environment. We are happy to see that IE has proven its capacity and performance on multimillion-gate SOC designs. We have successfully used IE and its integrated hierarchical database to design and tape-out a multi-million transistor chip in our 0.12-micron technology. We are now putting IE in use for production mixed analog-digital designs of up to 100 million transistors in this same 0.12-micron technology.”

IE is available for limited release on UNIX-based workstations. The 1-year U.S. list price for a time-based license (TBL) starts at $600,000.


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