TOKYO — Looking to overcome a major roadblock of the ITRS (International Technology Roadmap for Semiconductors) Hitachi and IMEC plan to develop manufacturable gate-stack processes needed for (sub)-70nm devices.

The three-year agreement, the two companies will work to develop a new gate stack, including cleaning and contamination control, deposition of high-k dielectrics using ALCVD (atomic-layer chemical vapor deposition) and MOCVD (metal-organic CVD), physical and characterization of high-k materials, reliability of gate stack and transistors, metal gates, process integration issues and environment, safety and health considerations.

As semiconductor devices shrink, traditional processes and materials are approaching their physical limits. To take advantage of the reduced design ruled of the ITRS, the industry is moving to thinner effective gate dielectrics for (sub)-70nm devices.

“The semiconductor industry has been built on silicon dioxide,” said Gilbert Declerck, president and CEO of IMEC. “We are now facing a point where the heart of the MOS transistor has to be replaced.”

“The only way to overcome this major roadblock of the ITRS is by coordinating these newgate stack activities on a global scale, by sharing cost and risk, and by combining expertise,” Declerck added.

A Hitachi researcher will be stationed at IMEC for the duration of the agreement.