February 23, 2001–Tokyo, Japan–Hitachi Ltd. has joined Belgium-based independent research center IMEC’s industrial affiliation program on high-k dielectrics with the goal of overcoming one of the major roadblocks of the International Technology Roadmap for Semiconductors (ITRS). IMEC and Hitachi will cooperate for 3 years on the development of gate-stack processes needed for sub-70nm devices.
As semiconductor devices continue to shrink, conventional processes and materials approach their physical limits. To take full advantage of the reduced design rules of the ITRS, the industry must move to thinner effective gate dielectrics for sub-70nm devices. Silicon dioxide is unable to perform at these reduced thicknesses because of excessive leakage and reliability problems.
The program will include all aspects required to develop the new gate stack–deposition of high-k dielectrics using atomic-layer chemical vapor deposition and metal-organic chemical vapor deposition, cleaning and contamination control, physical and electrical characterization of high-k materials, reliability of gate stack and transistors, metal gates, process integration, and health and safety issues. The initial effective oxide thickness (EOT) targeted is 1nm, although the final goal is a feasibility demonstration of 0.5nm EOT gate stack.