National develops 10:1 bus LVDS serializer/deserializer chipset with two modes of system test access

Santa Clara, California–National Semiconductor has developed a 10:1 bus LVDS serializer/deserializer chipset with two modes of system test access. The SCAN921023 and SCAN921224 provide IEEE 1149.1 boundary scan test access to the digital TTL side of the devices, while at-speed Built-In Self-Test (BIST) verifies the interconnects at the high-speed system frequency of the LVDS channel.

“System bandwidth will expand at an ever increasing rate as the telecommunication industry, especially manufacturers of 3G mobile phone base stations, continue the trend to integrated data, voice and video streams,” said Guy Nicholson, marketing director of National’s Interface Group. “LVDS technology can support these bandwidth demands. But at these speeds and transfer rates, boundary scan test access and at-speed BIST are the only reliable tests to verify hardware interconnects in dense backplanes.”

When the RUNBIST instruction is executed in the SCAN921023 and SCAN921224, the chipset automatically synchronizes and performs a pseudo-random bit sequence (PRBS) bit error rate test (BERT). The serializer generates the pseudo random pattern and the deserializer detects the bitstream and compares it to the expected pattern. “Test completed” and “pass/fail” flags indicate bit errors are less than 10-7. Since the SCAN921023/1224 create a very high speed interconnect, RUNBIST is needed to check for faults (e.g. capacitance) that would not otherwise be caught using standard 1149.1 EXTEST methods alone.

National’s LVDS chipset efficiently speeds data around the digital infrastructure of dense backplanes by serializing as many as ten parallel data bit streams and embedding the clock, then deserializing the signals to recover the clock and data for delivery to the parallel receiver interface. It is the only serializer available capable of driving a 20-slot backplane. Moreover, the deserializer can be inserted into pre-existing data streams with random data, allowing “hot insertion” of cards. This high-speed data transfer over a single differential wiring pair–from 200 to 660 Mbps–cuts system cost by shrinking printed circuit board area and minimizing cable and connector width. With the lowest power consumption of any similar product–just 600mW at 660Mbps–it also lowers power dissipation, eliminates the termination power supply, and reduces cooling system requirements.

The chipset allows users to bus data to multiple deserializers or to send data point-to-point, and provides the bandwidth necessary to transfer digital data from the RF converter to DSP baseband processing units.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.