Smaller footprints free up space for added functionality or product miniaturization
BY TIM SAMMON
New power and protection devices in wafer-level packaging (WLP) are aiding in the overall reduction of size and weight of portable equipment products. Such devices can deliver the same performance that is available in larger formats, but in footprints that are 30 percent of traditional surface mount technology (SMT) components.
Today's smaller, lighter, more capable portable devices, such as wireless phones and internet pagers, global positioning system receivers, or personal digital assistants (PDAs), require large battery packs to deliver acceptable operation times. The trade-off between battery pack size and product operating times has focused designers on maximizing energy storage density. This has resulted in a move to lithium polymer cells, forcing the miniaturization of the protection circuitry that this chemistry requires.
Shrinking the metal oxide semiconductor field effect transistor (MOSFET) charge/discharge control devices in a circuit can result in up to a 20-percent smaller battery outline or more volume for additional energy storage for up to 30 additional operating minutes on a three-hour battery. Meanwhile, competitive demand for added functionality in these products is fuelling increases in IC usage and power requirements. Of course, this needs to be delivered in the same case, so board space is finite and costly. Therefore, enabling the same load management performance in one-third of the footprint once required allows for added functionality or product miniaturization.
Figure 1. WLP device form factor.
Just how small a power product can go in size, design and package primarily depends on its function, which is to carry current. Newer designs tend to deliver better performance, an advantage where overall size can remain static, or can provide equally or incrementally better performance in much smaller packaging.
Designing a wafer-level package presents several challenges (Figure 1). It must fit into a conventional SMT assembly process and also be resistant to moisture penetration, both for reflow and long- term reliability considerations. Additionally, it is desirable not to require tertiary processing, such as underfill, to complete the assembly.
Surface Mounting: The solder bump interconnect pitch of 0.8 mm of the WLP is in accordance with the standard JEDEC definition of a CSP footprint and, hence, avoids any requirement for fine-pitch substrates. Stand-offs enable clean or no-clean fluxing processes to be used at board mount.
Moisture Protection: In most devices, including substrate-based and the emerging leadless package CSP forms, a plastic package surrounds the die to prevent moisture intrusion. WLP without this extra packaging protects against moisture and other environmental intrusions at the wafer level.
Figure 2. Under-bump metal structure eliminates moisture ingression.
To this end, a silicon nitride passivation layer can be used as the last masking process in wafer fabrication, so vulnerability is localized to the exposed metal used for interconnect via the solder bumps. Moisture intrusion here is addressed by a mechanical structure of an under-bump metal (UBM) layer (Figure 2). The nature of the electroless nickel deposition process gives an even, flat deposit, mirroring the surface of the top metal. The metal grows equally in horizontal and vertical directions, giving an overlap of the passivation layer. This can provide a tight mechanical seal that prevents ingress of moisture into the device.
An electroless nickel layer also prevents diffusion of the wafer metallurgy into the solder bump and provides a surface to which the solder bumps adhere. A thin layer (~ 0.1 µm) of immersion gold over the nickel finishes the UBM, preventing oxidation and providing a solderable surface finish.
Figure 3. ZΘ curve for a 1.5 mm2 , 65 mΩ wafer-level packaged MOSFET.
In contrast to conventionally packaged devices, this passivation is not vulnerable to moisture uptake in the same manner as epoxy encapsulation; therefore, popcorning during reflow does not occur using WLP.
The Question of Underfill: Reliability testing has shown that commercial reliability levels can be achieved without the use of underfill on the device shown in Figure 1. As the size of a device increases, the effect of joint fatigue induced by temperature cycling increases.2 This infers that there will be a device size at which underfill will be required to achieve reliable assemblies on organic substrates. Work is underway to identify the size at which this occurs.
Thermal Performance: With any power device, thermal considerations are a priority in design. A WLP MOSFET has similar performance profiles as devices that are much larger. Thus, the theoretical heat dissipation per area can be much higher with WLP devices than traditional devices. Figure 3 illustrates this by showing the ZΘ curve for a wafer-level packaged device (in red).
One of the first applications of miniature MOSFETs was a battery-protection device that prevents the overcharging or discharging of a lithium-ion battery. This circuit is usually incorporated in the battery pack, so size was a concern.
Figure 4 shows a typical battery pack assembly with a total volume of 1.06 inch3. It is designed with the battery protection circuit assembly using traditional small-outline integrated circuit (SOIC) packaged devices. The battery measures 1.38 x 1.86 x 0.34 inches for a volume of 0.873 inch3. The flex circuit protection assembly measures 1.38 x 1.86 x 0.073 inches for a volume of 0.187 inch3 or 17.6 percent of the total volume of the battery pack. In addition, the SO-8 controller and MOSFETs are the tallest components on the board.
Figure 4. Typical battery pack circuit.
By using a WLP bi-directional MOSFET switch and a battery monitor/controller flip chip, less volume is needed so the protection circuit can fit on the edge of the battery (Figure 5). With the tallest component being a capacitor, the assembly measures 1.38 x 0.34 x 0.05 inches for a volume of 0.0235 inch3 or 2.6 percent of the total volume. With 15 percent more volume available, this space could be used for added energy storage, increasing talk time 15 percent, or to shrink the battery pack outline and reduce the size of the cellular phone.
Another application is the transient protection circuit on the actual circuit board of cellular phones and PDAs. These transients are particularly challenging for devices with rechargeable batteries. Electrical systems often suffer from transient voltages, or surges. Transients can damage every type of electrical equipment, from sensitive electronics to heavy industrial motors.
Figure 5. WLP circuit design with up to 20-percent size reduction.
Valuable real estate is used on the input power circuits (+5, +12) to eliminate these transients. A typical transient suppression circuit for a hand-held device using current TSOP-6 MOSFET devices uses over 20 cm2 of board space.
A new circuit exhibits the same protection specifications and functions using WLP devices. Overall area is reduced to fewer than 10 cm2, a savings of greater than 33 percent.
Elimination of device packaging, and therefore resistance and inductance losses related to the package, allows for a much smaller MOSFET device footprint for a given RDSON. Also, the improved thermal dissipation per footprint area allows designers to design higher power densities than have been previously possible using standard TSOP-6 and SO-8 devices.
- D. Kinzer, D. Asselanis and R. Carta, “Ultra-Low Rdson 12V P-channel Trench MOSFET,” Proceedings of the International Symposium on Power Semiconductor Devices and ICs, May 1999.
- J.H.Lau, Solder Joint Reliability, Van Nostrand Reinhold, 1991.
TIM SAMMON, director of packaging R&D, can be contacted at International Rectifier, +44 1883 733396; Fax: +44 1883 733408; E-mail: [email protected].