March 13, 2001–Munich, Germany–Responding to escalating concerns that the cost of testing complex semiconductor devices may soon exceed the cost of fabrication, Synopsys, Inc. and Agilent Technologies Inc. today announced an agreement targeted at reducing the overall cost of test by bridging the gap between electronic design automation (EDA) test software and automated test equipment (ATE) hardware.

Both Synopsys and Agilent recognize that the future of affordable, high quality manufacturing test lies in strong coordination between ATE companies and EDA tool providers. This agreement establishes a framework for close evaluation of potential innovations in test technology for new and existing worldwide customers as they seek to bring complex system-on-a-chip (SoC) devices to market.

Rapid growth in SoC designs has led to the proliferation of complex, high pin-count devices that are dramatically more difficult and expensive to test. As a result, both companies are facing a strong mandate from customers to resolve this situation. In response, Synopsys and Agilent will explore the ability to make EDA test tools aware of intended ATE environments for SoC devices in order to synthesize the optimal design-for-test (DFT) structure. Moreover, ATE hardware must have the ability to fully use every DFT resource available on the device.

“This strategic alliance, the first of its kind, clearly positions Agilent and Synopsys at the forefront of the system-on-a-chip era where design and test must be linked,” says Tom Newsom, vice president and general manager of Agilent Technologies’ System-on-a-Chip Business Unit. “We aim to provide our customers with huge benefits in time-to-market and cost-of-test savings from our initiatives that shatter the wall between design and test.”