March 22, 2001 – Santa Clara, California – Applied Materials has introduced a CVD TiSiN (titanium silicon nitride) barrier process. According to Applied, the CVD TiSiN process provides customers with an optimized single system solution for the development of future sub-0.1 micron copper/ultra-low k chip designed on 200mm or 300mm wafer, when combined with an established SIP PVD Cu seed chamber on the Endura Electra Cu Integrated Barrier/Seed system.

The barrier process was created to provide good step coverage on the rough or uneven interconnect sidewalls which are presented by the porous ultra-low k dielectric materials. The low temperature process is said to enable greater than 85% bottom and sidewall coverage in a small, high aspect ratio feature. Applied said that this process allows high copper conductivity of the interconnect structure, while providing an excellent barrier to prevent copper diffusion into other areas of the device.

According to Dr. Fusen Chen, VP and group general manager of Applied Materials’ Cu, PVD and Integrated Systems and Modules Business Group said, a number of CVD TiSiN chambers have been shipped to customers in Asia, and in the US. They are being used for the development of both logic and memory devices, Chen said.