March 8, 2001–Fremont, California–Chartered Semiconductor Manufacturing and Virage Logic Corp. have announced efforts to develop Virage Logic’s Custom-Touch ASAP embedded memory compilers for Chartered’s all-copper, low-k dielectric, 0.13-micron “communications-smart” manufacturing process. The agreement provides chip designers using the new Chartered process with enhanced performance and accuracy for designs containing embedded memory.
Chartered’s communications-smart technology strategy, which is tuned to the needs of the high-growth and technically demanding communications segments of the electronics industry, requires an application-specific approach to dealing with memory-intensive chip designs typical of today’s high-speed and mobile communications products. Virage Logic’s ASAP embedded memory is optimized for density, speed, and low power. The companies’ relationship will enable Chartered’s customers to gain access to Virage Logic’s offerings, which are intended to provide improvements aimed at enhanced reliability and manufacturability.
In order to achieve the highest level of system reliability and to keep power consumption in the idle state as low as possible to extend battery life, Virage Logic has made several architectural improvements to minimize gate leakage current and to keep idle power consumption under check. For instance, Virage Logic has designed more robust memories with detailed layout guidelines. In addition, the company has included proprietary technology that minimizes the possibility of data corruption through the addition of sense amplifiers that operate at the lower voltages typical of the 0.13-micron process.
“Chartered was the first foundry to work with Virage Logic, and we remain committed to working with them as we advance our process technology,” says Michael Buehler-Garcia, vice president of marketing and worldwide EDA at Chartered. “The production-proven and reliable memory solutions they offer are of great benefit to our customers who value the efficiency and reliability of the Virage Logic family of embedded memories.”
“Chartered is a key partner for us and their communications-smart processes are a valuable way for us to reach important customers of our technology. The close working relationship we enjoy with their teams has allowed us to develop critical solutions for our mutual customers,” says Vin Ratford, vice president of marketing at Virage Logic. “We are pleased to be able to continue the progress we’ve achieved with earlier processes, and look forward to defining new and improved approaches in the future.”
Chartered, which has an extensive network of electronic design automation (EDA) and intellectual property (IP) partners, has reached an agreement with Virage Logic to jointly define a memory solution based on mutual customer input. These solutions are designed to consider such issues as redundancy and optimized core, bit-cell sizes. Previous generations of the Virage Logic compilers have been used successfully for designs manufactured with Chartered’s 0.35-micron through 0.18-micron processes.
Within the ASAP compiler family, Virage Logic has the following compilers available in the Chartered 0.13 micron process: 1- and 2-port register files, 1-port high-density SRAM and dual port high-density SRAM. The Chartered 0.13 micron design kit for early adopters is expected to be available in the first quarter of 2001, and target availability for silicon-validated compilers from Virage Logic is the third quarter of 2001.