Chip-level packaging

A system-level view


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CPU package design must start by addressing form factor. Whether for a high-performance desktop or a high-end workstation/ server, high-speed microprocessor packaging must be designed with the smallest form factor in mind. Microprocessor vendors are struggling with end-users' requirements for the highest performance in the smallest form, and for packaging engineers, this means addressing a growing challenge of power distribution, thermal management and EMI containment.1

The best solutions to these challenges will involve an integrated packaging architecture, which addresses the need to conserve space in the X, Y and Z axes. The ideal packaging architecture will also provide a common approach for many markets – value desktop, performance desktop, workstation and server – allowing the vendor to tailor functionality and cost. This becomes a significant challenge with increased demands on the power delivery and thermal dissipation solutions.

Power Distribution and Voltage Regulation

It is no longer feasible to deliver high-current, low-voltage power throughout a computer system from a central power supply. Power designers are turning to distributed power supply architectures in which power is bussed around the system at a high voltage and low current.2 Modular dc/dc converters (or voltage regulators) are mounted as close as possible to the microprocessor, converting the power to meet low-voltage, high-current requirements (Figure 1).

Figure 1. A distributed power architecture.
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Microprocessor vendors are researching the possibilities of incorporating voltage regulator circuitry into the CPU package itself to avoid unacceptable impedances and resulting voltage drops in the power distribution path. However, this is not yet feasible for a number of reasons, such as the unmanageable physical size of the power conditioning circuitry. In addition, increasing the number of analog components adversely impacts the processor reliability.

Figure 2. Power from the system to the package.
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There are various issues to consider in distributing power from the system to the CPU package. The need to lower thermal dissipation and improve device reliability for high-performance processors has resulted in the reduction of the power-supply voltage with each succeeding semiconductor generation.3 Unfortunately, the margin for error (transient-droop margin) is reduced with the lower operating voltages. The links in the power distribution path must have low impedance to minimize critical voltage fluctuations. For correct operation of the processor's circuits, the voltage seen at the CPU cannot vary more than 10 percent, which typically translates to a voltage regulator supply variance of only 5 percent.4

Figure 3. Current, slew and voltage trends.
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The real problem arises from transient currents. Computing demands vary because of high clock speed circuits and power conservation design techniques, such as clock gating and sleep modes. These techniques result in fast, unpredictable and large magnitude changes in supply current ultimately requiring hundreds of amps within a few nanoseconds. Unfortunately, the resulting current surge between the CPU and power regulator can create unacceptable spikes in the supply voltage (dv = IR + Ldi/dt).5 Values shown in Figure 3 for slew rate vary depending on where the change in current is measured and the total capacitance of the circuit, but the trend remains the same.6

Figure 4. CPU transient response at 1.0V operating voltage.
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Much effort is expended in placing power and ground planes and power and ground vias, and in capacitor pad design, to ensure low inductance power delivery loops. To gain the proper margin, as shown in Figure 4, surge currents are managed by placing many decoupling capacitors throughout the power delivery system – on the power regulation module, motherboard, die package and the die itself (Figure 1). This not only increases costs, but also consumes critical silicon area, chip package and board real estate. For microprocessors operating at more than 200 MHz, the most effective capacitor is an on-die capacitor or one that is physically very close to the die. All PC-processor manufacturers now use on-die capacitors.7

Thermal Management

The need for higher performance and an increased level of functional integration, as well as die size optimization, has led to higher heat-flux concentration in certain areas of the processor die. Engineers now foresee energy densities at the surface of the silicon approaching unmanageable levels. Heat-load and heat-flux keep climbing (Figure 5).8

Figure 5. Thermal heat-load and heat-flux.
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Reliability of the CPU is exponentially dependent on the operating temperature of the die junction. Lowering temperatures 10 to 15

Thermal engineers must also take into account the nearby voltage regulator efficiencies. For example, a voltage regulator working at 85 percent efficiency driving a 130-watt device dissipates over 20 watts. Therefore, trying to locate the voltage regulator close to the CPU (an important goal) becomes more difficult as CPU performance increases.

Figure 6. Battle between thermal and EMI for aperture size.
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As thermal densities increase beyond 60 W/cm2, more effective heat spreading technologies, such as vapor chambers, will be necessary. With these technologies, the heat-dissipating device effectively becomes isothermal. Thus, rather than managing both the processor and its power source independently, the ideal thermal architecture would service both taking advantage of a single isothermal structure. This would allow the CPU and its power source to be more easily integrated.

EMI Containment

The microprocessor is by far the largest source of electromagnetic energy. Containing radiated and conducted emissions at the source (at the CPU package) would make the system design easier for computer OEMs. To comply with FCC regulations, the system must be tested for emissions at up to five times the CPU operating frequency or 40 GHz, whichever is lower. This is necessary because of the harmonics that are generated from the base CPU frequency.

The main component of EMI is a radiated electromagnetic wave with a wavelength that gets smaller as frequencies increase. Chassis-level solutions involve reducing the size of openings in the system, effectively blocking the waves. However, the solutions are more challenging when apertures need to be reduced for EMI, but increased for airflow (Figure 6).

Figure 7. An integrated packaging architecture.
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Heatsink grounding may be another effective way to reduce system EMI emissions. Noise coupled from the processor package to the heatsink may cause it to act as an antenna and re-radiate the noise. However, grounding the heatsink through the CPU package is not possible with most implementations.1 In addition, grounding of heatsinks may reduce EMI, but that alone may not be sufficient to pass the required tests. Additional shielding of the processor itself may be necessary.

Tomorrow's Microprocessor Chip Package

Each generation of microprocessor packages transforms into an even more sophisticated thermal, electrical and mechanical platform. Tomorrow's microprocessor package must take into account all system-level implications in an integrated approach.

Figure 8. A CPU packaging approach.
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A modular “On-Package-Voltage-Regulation” (OPVR) architecture provides a much-needed solution. Modular OPVR couples the performance benefits of integrating voltage regulation with the CPU with the benefits of making the voltage regulator an independent and modular device. Having the voltage regulation next to the chip eliminates the path impedance and need for much of the capacitance. Until recently, however, no apparent solution existed for interconnecting the voltage regulation circuitry on the package in a modular approach, especially given the physical size constraints of today's CPU packages and their associated power interconnect solutions. Voltage regulators are currently interconnected to the processor through bulky high-pin-count edge-connectors.

This packaging design integrates the microprocessor with its voltage regulator into one single modular construction – modular OPVR (Figure 7). Miniaturized power circuitry is mounted on the underside of a power substrate that houses the DC/DC components and acts as a heatsink grounding structure and common-mode current shunt. The heat-dissipating device is used for both the processor and power circuitry. A photograph of the CPU package itself is shown in Figure 8. Not shown is a motherboard-mounted EMI frame that functions as a faraday cage for the processor, voltage regulator and heat dissipating device.

This architecture addresses several system issues, including reducing the power interconnect impedance by virtually eliminating the path between the power source and the load. Cleaner power translates into large signal-to-noise margin, resulting in higher operating frequencies. This approach also addresses the issue of providing a cooling solution for both CPU and VRM. Rather than leaving the thermal solution for the OEM in two discrete parts, this design forces a single design. This can translate into lower junction temperatures, resulting in higher operating frequencies and/or reliability figures. The power substrate itself provides a good groundling and shielding structure for higher shielding effectiveness. Package designers can only benefit by investigating a system-level view to chip-level packaging.


  1. Polka, et al., “Package-Level Interconnect Design for Optimum Electrical Performance,” Intel Technology Journal, Q3, 2000.
  2. Kaskade, “Power Distribution for High-Performance Processors,” High-Density Interconnect, October 2000, Vol.3 No.10.
  3. “International Technology Roadmap for Semiconductors,” 1999 Edition, Semiconductor Industry Association.
  4. Baliga, “Power, EMI and Thermal Management in One Unit,” Semiconductor International, September 2000.
  5. Herrell, “Processors Put Pressure on Packages,” Microdesign Resources, December 27, 1999.
  6. Chickamenahalli, Li and Figueroa, “Study of Synchronous DC/DC Converters in High-Current Processor Power Delivery Systems,” 2000 International Conference on High-Density Interconnect and Systems Packaging.
  7. Diefendorff, “Processors Penetrate Gigahertz Territory,” Microdesign Resources, February 28, 2000.
  8. Tadayon, “Thermal Challenges During Microprocessor Testing,” Intel Technology Journal, Q3, 2000.
  9. Viswanath, Wakharka, Watwe and Lebonheur, “Thermal Performance Challenges from Silicon to Systems,” Intel Technology Journal, Q3, 2000.

JIM HJERPE KASKADE, president and founder, can be contacted at INCEP Technologies, 10650 Treena Street, Suite 308, San Diego, CA 92131; 858-547-9925; Fax: 858-579-9926; E-mail: [email protected].


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