Monthly Archives: March 2001

Why reuse?


March 1, 2001

BY DANIEL K. WARD

The term reuse is commonly defined as using something again after some special treatment or processing. Today, it has become socially acceptable to reuse many of the things we have created and mass-produced. In fact, in terms of environmental awareness, reuse is seen as a desired method of reducing the depletion of natural resources, including the significant amount of energy required to manufacture new things. Some typical examples of reused items are homes, automobiles, clothing, furniture, books, compact discs and videotapes. Reuse must not be confused with recycle, which generally refers to the extraction of useful material from garbage or waste.

It's a Matter of Planning

So why am I writing about reuse in a technical magazine? The answer is simple: Much of what a company's engineering organization produces can be reused by planning and organizing properly. This can result in increased productivity and dollars saved. The key word here is “planning.” A concise engineering definition of reuse that we use at Delco is the planned creation, development, verification and documentation of standard building blocks that can be leveraged repeatedly and applied quickly to specific customer product requirements.

In most companies today, however, reuse is informal. Reuse building blocks (electrical, mechanical, software, manufacturing, systems, etc.) are usually not common across products. Many different methods are used with minimal planning, strategy and object management. Therefore, the benefits of reuse tend not to be realized company-wide.

Benefits: What are some of these reuse benefits? First of all, if company knowledge is stored and made available enterprise-wide, duplication of engineering efforts on various products can be minimized. Therefore, product development cycle time to the customer is reduced. Also, the amount of materials and components needed within the company is reduced, which simplifies purchasing and material control. Overall quality can be improved by reusing successful designs and processes, and quicker, more accurate customer quotations are possible. In the end, all of these benefits result in lower product development and manufacturing costs.

The Building Blocks

As with any new concept, there are procedural changes that must be made to implement reuse, and this, of course, requires planning. Once you determine the building blocks critical to your products, you must plan their evolution over time. This means to strategize and design building blocks that meet anticipated future customer and internal requirements. While this is not an easy task, useful technology strategies and roadmaps can and must be developed. New building blocks then must be designed to meet cost targets, and be confirmed as functional, buildable and reliable. Only then will they be sought out and used effectively in products.

There are seven major steps to make a reuse strategy succeed:

  • Define required reuse processes, incentives and commitment
  • Plan and develop building blocks in anticipation of need
  • Develop building blocks on schedule
  • Store building blocks in a company-wide library with search/query capability
  • Building blocks must include a thorough applications document
  • Confirm/validate building blocks to actual requirements
  • Design the building blocks with commonly used processes and tools.

There are also hierarchical levels of building blocks. Starting with knowledge as the broadest building block level, it is then important to consider components, subsystems and assembly. You have the greatest opportunity for reuse with knowledge, and the least with assembly. Conversely, the greatest work savings occur at the assembly level. Each company should determine what level of reuse to seek for their particular product mix.

Building blocks also come in families. Examples of these families include system, software, electrical design, mechanical design, manufacturing and test. Each of these families consists of many building blocks. For example, in the manufacturing family, there might be surface mount technology, soldering, package, assembly, labeling, test, plastics, sheet metal and diecast. Elements of a typical building block, like labeling, include label type, label construction, what it will be applied to, application equipment, application method, verification method, reading method and removal method.

The Obstacles: Now, assuming that the concept of reuse has been adopted with building blocks, what is the biggest barrier to success? In my opinion, it's information technology. For a building block to be reused, it must be easily found. In most companies, reuse information resides in various unlinked data systems. These systems must be linked and facilitated by a search/query tool. This tool must be simple and intuitive to use, or else the system will not be used.

In the End

In summary, reuse is a powerful concept. It can save time, reduce cost, improve quality and increase reliability. To be effective long-term, reuse requires a product and design strategy that provides the time for a building block to be designed and confirmed as functional, manufacturable, reliable and cost-effective. All this must be completed before a product's initial application to take advantage of reduced product design times and, thus, be quick to market with new features on multiple products.
AP

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DANIEL K. WARD, manager of advanced electronic packaging, can be contacted at Delphi Delco Electronics Systems, One Corporate Center, P.O. Box 9005, Mail Station: D-16, Kokomo, IN 46904-9005; 765-451-3093; Fax: 765-451-3115; E-mail: [email protected].

Flip chip

The decision to use flip chip packaging is not a simple one. Many equipment, product, and process variables affect the relative merits of flip chip vs. wire bonded packages. A detailed analysis of all of these factors can help to guide the decision and clarify the effects of the variables on the cost of different packaging approaches.

Wire bonded packages have been used for many years, and today more than 95% of all packages assembled are with wire bonding technology, primarily because the high-speed wire bonders meet most of the interconnection needs of semiconductor devices. However, the past few years have witnessed an explosive growth in solder bumped flip chip ICs on low-cost organic substrates, and the growth will be more than 20%/year by volume over the next five years, according to TechSearch International, a consulting firm that specializes in advanced packaging. This growth is a direct result of the requirements of greater package density and higher performance, as well as the limitations of wire bonding. In comparison with wire bonding technology, flip chip technology provides higher packaging density (more I/Os), higher performance (shorter possible leads, lower inductance, and better noise control), smaller device footprints, and lower packaging profile. The advantages and disadvantages of the two technologies are presented in the table on page S20.

Is flip chip cost-effective?

Once an engineer decides that the performance advantages of flip chip outweigh the benefits of wire bonded BGA/CSP packages and has addressed the logistics of changing over to flip chip technology, he/she then needs to consider whether flip chip is a cost-effective solution. What is the cost comparison between a solder bumped flip chip package and a wire bonded BGA? The answer to this frequently asked question is not simple.


Figure 1. Process flow for flip chip BGA and wire bonded BGA/CSP packaging.
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The cost of flip chip packaging depends on many factors, which can be categorized as: die and wafer-level issues, type of flip chip bumping technology used, die cost (e.g., microprocessor vs. memory), package assembly flow, and process cost of ownership.

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Under each of the above headings, there are many variables that affect the final flip chip packaging cost. Let us review each one and see with a sample calculation the cost of flip chip packaging compared to BGA/CSP packaging. Similar cost comparison calculations can be made to compare flip chip and other packages, such as TQFP, PLCC, or TSSOP.

Die and wafer-level issues. The flip chip bumping process is a wafer level process, and therefore any cost comparison with a wire bonded BGA/CSP type of package must be done from the wafer level. For example, the number of die on a wafer depends on the bond pad pitch and bond pad configuration on the die. A large bond pad pitch can force a die to be larger to accommodate the bonds, which results in fewer die/wafer. Similarly, if the bond pads are configured in a peripheral format or staggered format, then the die size can be much bigger compared to an area array format on the die. The bond pad size and configuration can have a direct impact on the number of die that can fit on a wafer.


Figure 2. Wafer information for flip chip BGA and wire bonded BGA/CSP packaging.
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Die yield at wafer level. When the wafers are subjected to wafer-level electrical testing, the products with lower die yield will have a significant impact on the flip chip packaging cost. If the wafer's electrical yield is low, more wafers need to be bumped to achieve the same production volume of the final packaged device. With wire bonded packages, only the devices that are identified as good at the wafer level go through the packaging process. This screening is not possible with wafer-level packaging approaches.

Type of bumping technology. Today there are five major types of bumping technologies: screen printed, electroplated, electroless, evaporated, and solder bump with wire bonder.

There are technical and economic advantages and disadvantages with each of these bumping technologies. For example, screen-printed solder bump technology is an economical process technology, but the minimum pad pitch has to be 150µm. Conversely, the evaporated bump technology can give very fine pitch area array pads, but the cost of the process is very high.

Impact of cost of die. Since the bumping process is at the wafer level, yield losses at the wafer bumping step will increase the cost of the flip chip packaging process. The wafer bumping yield loss could be due to many things, including: the wrong process, different materials, bump height nonuniformity, low bump shear strength, broken wafers or die, solder bridging, and missing bumps.

One must recognize that any bumping technology requires significant effort to optimize it for any particular wafer technology. It should also be noted that solder bumps are not reworkable. Bumping has to be right the first time.


Figure 3. The cost of a wire bonded BGA/CSP packaging approach is affected by a) equipment availability, b) equipment throughput, and c) variable costs.
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Assembly process flow. Flip chip bumped die can be assembled into final products either by direct chip attach (DCA) or by assembling as a BGA package (FCBGA). The use of bumped die as DCA is still not very common. FCBGA is today more common. The assembly process flow for FCBGA is shown in Fig. 1, along with wire bonded BGA/CSP flow. Generally speaking, the number of processes is an indication of the packaging assembly cost.

Process cost of ownership. One can calculate the cost of flip chip packaging compared to wire bonded BGA/CSP, taking into consideration the process cost of each approach. Each assembly process has a cost associated with it, which depends on: production volume, equipment cost and depreciation schedule, equipment uptime and availability, equipment throughput, fixed costs, manpower cost, variable cost, and yield cost.

Estimation of packaged device cost

From the above discussion, we can see that the comparison of costs between a flip chip BGA and wire bonded BGA is not a simple calculation, but involves a host of parameters that need to be incorporated, beginning from the wafer level. The actual cost of the final package is a combination of all the above costs.

Let us take an example and study the variation in packaging cost for FCBGA and wire bonded BGA as a function of variables such as die cost, number of I/Os, wafer level die yield, and assembly process yield.

Suppose we consider a wafer with a diameter of 200mm, 200 I/Os on each chip, $5 average die cost, and an expected die yield at wafer-level electrical testing of 60%. Now let us compare the packaging cost of a FCBGA package with area array bumps with a pitch of 150µm, and a wire bonded BGA with peripheral bond pads with a pitch of 80µm. The values are all entered in Fig. 2. One can see the number of possible good die on a 200mm wafer.


Figure 4. Summary of the cost for each process step for flip chip BGA and wire bonded BGA/CSP packaging.
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Suppose we have a planned production volume of one million devices/month, and the packages have to go through the assembly processes as described in Fig. 1. We can calculate the total assembly cost of packaging. The cost of each process depends on the previous process and the yield obtained from that process. Let us take the example of the wire bonding process and calculate the process cost.

The wire bonding process requires a wire bonder at a cost of approximately $100,000/machine with a life of five years. Major contributors to process cost are equipment uptime and availability, which depend on mean time between assists (MTBA); mean time to assist (MTTA); mean time between failures (MTBF); mean time to repair (MTTR); scheduled maintenance time; standby time; and production change-over time (Fig. 3a).

The equipment throughput depends on factors such as bonding speed, pad recognition time, device handling time, lead count (in the case of wire bonding), and expected process yield (Fig. 3b).

The variable cost is calculated taking into consideration the length of the gold wire, the cost of gold wire, capillary life, and capillary cost (Fig. 3c).

When similar process cost calculations are performed for all processes in the flow, one can obtain the total cost of the package. The result is shown in Fig. 4.

Effect of die cost, I/O count, and die yield

An analysis of the dependence of packaging cost on die cost is shown in Fig. 5a for three different values of assembly yield (99%, 99.5%, and 99.9%). As the die cost increases, the cost of packaging increases, and when the die cost is $20, the flip chip BGA cost with a 99% assembly yield is three times higher than a wire bonded BGA/CSP with a 99.9% assembly yield.

At lower I/O counts, the wire bonded BGA/CSP is an economic solution, but as the I/O count increases, the cost of wire bonded packaging increases dramatically. The cost-effectiveness of flip chip vs. wire bonded approaches is a strong function of the number of I/Os on the chip (Fig. 5b).


Figure 5. Cost/package for three values of assembly yield as a function of a) die cost, b) number of I/Os, and c) die yield at wafer level.
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If the true die yield increases (higher number of electrically good die on the wafer), the flip chip package cost decreases. Figure 5c shows that as the yield increases from 40% to 80%, the cost of FCBGA is reduced by almost 20%. The impact is higher at higher assembly yields. The wafer level die yield has almost no impact on wire bonded BGA packages.

Conclusion * The change-over from existing wire bonded BGA, CSP, TQFP, or TSSOP packages to flip chip packaging needs a thorough cost analysis. Factors that need to be considered include bond pad pitch, bond pad configuration on the die, die yield at wafer level, die cost, bumping technology, the assembly flow, and the process cost of ownership.

Many decisions, such as bond pad pitch, bond pad configuration, and type of bumping technology, need to be made before the die is even designed. Therefore, it is highly recommended that software available in the market be used to analyze the impact of all of these variables to make an educated decision about when to implement flip chip technology.

Acknowledgments

The authors thank Keshav Prasad for his assistance with software design and Ashwini Pradhan for her assistance with software quality testing and validation.

Shankara Prasad, APT Interactive, 235, 40th Cross, 5th Block, Jayanagar, Bangalore, 560 041 India; ph 91/80-665 7277, fax 91/80-663 9214, email [email protected].

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Packaging

Despite the many advances in assembly manufacturing since the IC was invented, the basic process has not changed significantly. This article reviews the steps used to assemble an IC at a foundry: wafer dicing, die bonding, wire bonding, encapsulation, lead finish, marking, singulation/lead forming, and packing.

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IC devices are fabricated on a variety of materials, most often in wafer form. Wafers typically arrive from a fabrication site in single or multiwafer carriers that protect them during shipment.

At some foundries, upon arrival, wafers are manually inspected under magnification for any defects that may have occurred after fabrication, either during electrical wafer probe or in shipment. Unfortunately, manual inspection, often known as “first optical inspection,” can also produce defects. Since defects drive low yields and higher costs, this preliminary step is often skipped.

Wafer dicing

Because die thickness can impact several downstream process steps, a wafer is first thinned to the appropriate thickness – from 2-25mils – before dicing.


Wirebond clamp and head assembly for a PBGA.
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During wafer dicing, the thinned wafers are mounted, with their active surfaces exposed, onto the center of release tape fixed to a steel ring. Automated equipment batch-processes the wafers centered on the release tape from magazine to magazine, placing them in the middle of the steel ring. From this point, the output magazine from the taping machine is sent to the input of the wafer saw.

The wafer saw, consisting of a blade embedded with diamond particles that rotates at a very high speed, passes through the wafer at boundaries between die known as saw streets, which are established during wafer fabrication. The dicing machine is programmed to drive the saw blade through the saw streets at a defined spindle speed, saw rate, and depth, separating the wafer into individual die.

A variety of sawing techniques can be used during the dicing step, including multigang arbors that can cut multiple swathes through the wafer, thus accelerating the process; variable depth passes that can enhance yield but may slow processing; and dual in-line arbors that allow multidepth passes to happen in a single pass. Other packaging styles call for dicing to singulate individually finished packaged die, a near-end rather than a beginning processing step in IC assembly.

Throughout the dicing step, a continual rinse of deionized water flushes the surface of the wafer, which remains free of saw debris that can interfere with processing and cause defects.

Die bonding

From the wafer saw process, die travel to die bonding, depending on their end use. The separated die are lifted off the release tape and fastened to a carrier frame of copper, alloy 42, palladium, ceramic, or an organic laminate substrate, depending on the type of package to be assembled. In this article, we use leaded copper packages most often as representative examples.

In today's high-volume manufacturing (HVM) factories, a frame can be single-site processed as a discrete unit throughout assembly or as a matrix of hundreds of units, batch-processed to achieve economies of scale. The frame material can differ, but in most HVM factories, units are processed in batches to achieve quality control and cost goals.


CABGA on a saw frame prior to singulation.
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An automated mechanism removes the die from the release tape by pushing it up and into a collected vacuum pick-up tool, which holds it and places it on the frame. During this process, the die is oriented to identify the first bonding location, a metallized pad on the surface of the die where it can be electrically connected to the package. The die-attach machine then dispenses a paste, film, or solder adhesive in a pattern that holds the die to the frame.

The frames, which are approximately 2 in. x 8 in. and may hold a few to several hundred individual die, are placed into magazines and cured before being moved to the next step, wire bonding. Individual magazines are placed in a clean, dry, air or nitrogen oven and then heated, allowing the paste (or other material) to cure and complete the adherence of the die to the frame. Curing temperatures, which may be as high as 200°C, and duration times, ranging from one minute to one hour, depend on the product, the materials being used, and the product's end-use. This is a bulk-processing step in which multiple magazines are placed in an oven at one time.

Wire bonding

At this point, the die is ready to be electrically connected to the frame. This is accomplished by thermosonically bonding a wire (typically gold) to the die. Wire bonding uses sophisticated equipment and software with a high degree of 3-D positional accuracy. Modern automated equipment can bond 11 wires/sec, depending on wire length, wire loop height, die-to-bond finger spacing, etc. The number of wire bonds/device can range from one to thousands, depending on die size and end use.


Wafer mapping at die attach.
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The frame moves from the magazine onto a heated plate, which aids in the bonding process, and the wire is threaded through a capillary that guides it to the surface of the die. The die is then vibrated ultrasonically, the metallurgy of the wafer determining time, frequency, and pressure applied. The wire is then drawn out and over the die and welded to the leadframe.

The die is now connected to the leads or pads that connect it to its end-use product. Alternatively, the die can be flipped active-side down and solder-welded directly to a frame or substrate. This is known as flip-chip bonding.

After wire bonding, epoxy underfill material, which improves long-term reliability, flows under the IC through capillary action and cures in a manner similar to die bond curing. While wire bonding is by far the most prevalent form of interconnection employed in the assembly of ICs today, input/output (I/O) densities and parasitic considerations are driving the need for flip chip bonding in many high-end applications.

After wire bonding, another sample optical inspection should be performed. Line operators look for missing or nonsticking wires, and perform several destructive tests on a representative sample of units. Individual nonconforming units are marked for removal at a later process step.

Encapsulation

After wire bonding, it is important to protect the IC package by applying molded encapsulation. A commonly used process is transfer molding, in which high temperature and pressure liquefies epoxy resin forced through a mold chase over the die and die frame and into the cavity on the frame where the die was placed earlier. The hardened epoxy forms the body of the final package.

In addition to transfer molding, the IC can also be encapsulated (or coated) in a liquid epoxy, which is cured to form a solid covering around the IC. In this case, the encapsulant only serves to protect the die and wires; it does not form the package body.

Controlling time, pressure, and flow are critical issues in the encapsulation step. Miscalculations can cause several problems such as wire sweep (wires pushed together causing a short circuit within the component), or partial molding and mold voiding, which are pockets (or bubbles) that form in the mold during the process.


Second optical inspection after saw.
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Laminate packages built on an organic substrate are also encapsulated in a process known as overmolding. As in a leadframe-packaged device, the die is attached to a laminate substrate. Unlike a leadframe package, where the molding process defines the package outline, the epoxy forms a “mold cap” that becomes the top half of a sandwich, with the laminate substrate forming the bottom half and the die in between. Similar sets of processing concerns exist for a laminate package, forcing attention to detail during the molding process to ensure a high-quality component.

Another die-protecting option is ceramic packaging, which uses the same initial process steps of dicing, die bond, and wire bond. In ceramic packages, however, instead of a molded cover, a cap of either ceramic or metal is welded or sealed over the die, encasing it in a sealed environment.

Lead finish

During lead finish, the copper leadframe is cleaned and plated with tin/lead solder. The frame, placed in-line on a conveyer, passes through a series of electrolytic baths, during which tin and lead molecules are attracted and attached to the device by an electrical charge given to the leadframe. The process controls concentrations of the deposits, which vary according to the product specifications.


Die epoxy dispense.
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Laminate packages are not typically plated. Two interconnect structures predominate laminate packages today: land pad and solder ball. In the case of a land pad, gold-plated copper pads are exposed on the bottom surface of the package. When the component is attached to a circuit card, solder paste coats the connection point on the card, which adheres to the land pad opening on the component. The circuit card is then heated to the melting point of the solder paste and the component is soldered in place.

Alternatively, spheres of 67/33 tin/lead are soldered to the land pads during solder ball attach. I/O density determines sphere size. Solder balls and flux are deposited on all pad locations on the strip in an automated two-pass operation. The equipment optically inspects the part to determine if all of the balls are in place. The strip then moves to a conveyer that transports it through a furnace that raises the solder to its melting point, wetting it to the pad.

Organic laminate can warp in this process, requiring strict control of the furnace environment to ensure minimum deformation of the substrate. The measure of the reflow condition to a reference plane is defined as coplanarity. A coplanar component is effectively flat, allowing it to sit on the circuit board and make contact. Tolerances to a few mils are maintained to allow for downstream processing of the component.

Marking

After lead finishing and ball attach, the part is marked. Marking or branding after molding, an often overlooked step, is important in the overall assembly process because it marks the part for quality assurance, date-coding the assembly and defining references to wafer and assembly lots. The mark can go on the bottom of the assembly, leaving the top available for a marketing brand.

Basic methods for marking use laser or ink. Laser marking is predominantly used in the industry today because of its high-quality repeatability. Ink marking suffers from cosmetic defects and rework concerns that can drive low yields.

Singulation and lead forming

The next step in the process for laminate packages is singulation, which is the process of excising single components from a strip or matrix. The leadframe package typically undergoes one more step before singulation, that of lead forming.


MQFP leadframe.
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Trim/form/singulate processes are combined to excise the component from the manufacturing strip. The copper leads, now plated with solder, are formed to allow placement of the part on a circuit card. Typically, the lead is formed straight, gull, or “J” bend. A straight lead is bent 90° to the die orientation, allowing for through-hole soldering. The lead is passed through a hole in the circuit card and is soldered in place to complete the connection. The solder plate on the lead eases this process. The gull-shaped lead is a surface-mounted part placed on the circuit card surface without a hole and soldered in place. A “J”-leaded part takes a straight lead and bends it under the package to form a J. Both gull and J structures are designed to take up strain induced by mounting the component on a circuit card. Care must be taken during the forming operation not to overly stress the lead, cracking the finish and causing corrosion. Once the lead is formed, the part is excised from the manufacturing strip.

Coplanarity is very important here. As the leads are formed, they become moveable objects. Flatness is critical for circuit card placement, so maintaining flatness across 256 (or more) leads is a delicate process that requires high-tolerance machinery. Only a 3mils difference in flatness is allowed in most process specifications.

Packing

The IC is now virtually complete. Final ality inspection and packing into shipment tubes, trays, or automated tape is all that remains. The completed component has traveled through as many as 150 steps, some highly automated. The total process could take from 2-5 days, depending on materials, product design, and purpose.


Saw singulation for CABGA.
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Not discussed here are the many inspection and cleaning steps designed to meet yield targets of greater than 99%. The industry, while essentially following the same basic process steps, has made tremendous improvements in the consistency and quality of the product that it assembles. Today's assembly facilities are nearly perfect, losing less then 50ppm to manufacturing defects, a quality rate that is critical for price-conscious customers.

Patrick McKinney is senior VP of marketing at Amkor Technology Inc., 1900 South Price Road, Chandler, AZ 85248; ph 602/821-5000, fax 602/821-6937, e-mail [email protected], www.amkor.com.

FLIP CHIP INTERCONNECT

COVER ARTICLE

Until recently, controlled collapse chip connection bump technology, developed in the late 1960s, provided a reliable interconnect for high-performance, leading-edge microprocessors. As device and wafer fabrication methods have progressed, however, evaporative bump technology has been increasingly unable to meet product demands. Electroplated bump technology, while not new, has emerged as one of the most desirable options currently available to meet increased interconnect requirements.


Motorola has developed electroplated wafer-bumping processes compatible with a range of bump compositions that enable fine pitch bumping, meet product requirements for higher I/O, bump over memory, and extend to 300mm wafer technology. Photo courtesy of Motorola Semiconductor
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For depositing bumps, electroplating offers the ability to reduce bump pitch, the flexibility to deposit different bump alloys, the capability to produce economical low-alpha bumps, and the potential to accommodate the demands of 300mm wafer processing. The technology's first three attributes can be instrumental in reducing overall system cost and enabling the migration of products from wire bond to flip chip, while keeping up with constant device shrinks. For 300mm wafer processing, electroplate offers a photo-based technology that can more readily accommodate the increase in wafer size.

As is usually the case with relatively immature technology, however, manufacturing electroplated bumps has its challenges. This article compares electroplate's attributes to those of evaporative bump technology, and describes challenges that could limit electroplate's widespread use.

Evaporated bump process

The controlled collapse chip connection (C4) evaporative bump process, patented by IBM in the early 1960s, provided a method for producing multichip modules for the mainframe computer market and single chip packages for high-performance computing [1].

The evaporative process deposits solder bumps by selectively depositing metals through a molybdenum (Mo) shadow mask. The initial process step is an argon (Ar) sputter etch to remove the die bond pad oxidation and ensure low electrical contact resistance. The evaporation of chrome (Cr)/chrome-copper (Cr-Cu)/copper (Cu)/gold (Au) forms the under bump metallization (UBM). This structure acts as a hermetic seal, provides an electrically conductive diffusion barrier, and establishes a good mechanical base for the solder bump.


Figure 1. Evaporative bump process.
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Following the UBM layer deposition, the next step is to evaporate lead (Pb), followed by tin (Sn), to form the bulk of the bump. In the unreflowed state, the bump heights are consistent across the wafer, providing a good interface for probing or burn-in. In the final step, the bump is reflowed, which homogenizes the PbSn solder and allows the Sn to form an intermetallic compound with the Cu of the UBM, providing the necessary adhesion between the die and the bump (Fig. 1).

Electroplated bump process

Some of the earliest bumps using electroplate as a deposition method appeared in the late 1960s and early 1970s with tape automated bonding (TAB) [2]. Gold was the most common material used for TAB bumps and the technology was primarily accepted by the Japanese for its high-productivity potential in the manufacture of low-cost consumer products like calculators and watches. Since that time, electroplate has seen numerous derivations of the original TAB gold bump process in the evolution of technology leading to bumped wafers for flip chip components [3, 4].


Figure 2. Electroplate bump process.
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An effective approach to the electroplate process for bumping wafers begins with a thorough cleaning of the wafer surface materials to ensure good electrical contact and adhesion of the bump to the wafer. After cleaning, the first metal layer of the bump's UBM base structure is sputtered on the wafer in blanket form. This first metal layer often uses titanium in combination with other refractory metals to provide optimum electrical contact to the device; this produces strong adhesion to the wafer surface constituents (polyimide, glass passivation, bond pad metallization, etc.), and acts as a diffusion barrier between the solder bump and the die metallization. Next, a thin metal seed layer, such as copper, is deposited in blanket form to provide a low-resistance electrical path for the electroplating process.

To define the remaining bump structures that are to be selectively electroplated on top of the sputtered UBM, a thick photoresist coating, align, expose, and develop process is performed. After the photo process, it is necessary to electroplate more copper to provide a mechanically stable base for the bump; the solder bump alloy of choice is then plated to complete the structure. After plating is complete, the photoresist is stripped and the UBM layers are wet etched away. Ashing, fluxing, reflowing, and cleaning complete the process (Fig. 2).

Evaporated vs. electroplated bumps

Bump pitch. Evaporated bump technology has extendibility issues when bump pitch is decreased below 225µm. The method used to fix the molybdenum mask to the wafer results in nonuniform clamping at the wafer edge and bowing of the mask across the wafer. Further, if the mask is not in physical contact with the wafer, metals can be deposited underneath, causing leakage or shorting between bumps. As bump pitch and diameters decrease, the mask must become thinner to accommodate the finer features. The thinner mask is thus not as rigid, which aggravates the nonuniform contact phenomenon. Another factor affecting fine pitch capability is the significant tolerance stack-up in the manual mask-to-wafer alignment procedure. This tolerance stack-up can prevent the UBM from covering the via, causing a nonhermetic seal and potential electromigration issues.


Figure 3. 100µm-pitch bumps.
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One of the most significant advantages of the electroplate bumping process is that it relies on photolithographic means to define the UBM and solder bump. Photolithography, in combination with a high-performance photoresist, permits extremely small structure definition and does not limit practical minimum bump pitch. For electroplate, bump pitch is limited more by assembly and reliability considerations than by the formation of the bump. Bumps have been successfully produced at 100µm pitch (Fig. 3). Figure 4 shows that, as device size decreases, bump pitch must also decrease to prevent possible die size increases for a given interconnect count.

Solder alloys and bump over memory. Evaporated bump technology is fundamentally limited to high-lead, low-tin solders, such as 95/5 Pb/Sn or 97/3 Pb/Sn, in the conventional Pb/Sn solder system. Tin possesses a relatively low vapor pressure, limiting the effective rate at which it can be evaporated. The unacceptable trade-offs are either long solder deposition times, or solder melting on the wafer because of excessive tin source power levels.

Electroplate, on the other hand, is not limited to high-lead, low-tin solders, and can quite readily process solders of any lead-tin composition as long as a chemistry is available. Electroplating is also adaptable to plating “no-lead” binary or tertiary alloys, which is becoming a requirement in many electronics assembly processes.

The electroplate process also provides a benefit for products requiring bump over memory. Bump over memory provides a way to minimize die size in situations where significant memory is on board the die. Bump over memory requires that low-alpha radiation materials be used in the bump to prevent soft errors and potential data corruption of memory cells. Lead is the primary offender with high-alpha emission levels relative to tin. Electroplate is a selective deposition process, so very little lead is wasted compared to evaporative technology. Therefore, electroplating of low-alpha-emitting lead is economically feasible.

300mm wafer-bumping capability. One significant challenge to wafer-level packaging development will be the introduction of the 300mm wafer. It is expected that high-performance microprocessors/memory will be the first to use 300mm wafers, which suggests that flip chip will be required when this technology is introduced. Today, evaporation technology does not appear to be extendible to 300mm wafers because of its dependence on molybdenum shadow masks. These masks have temperature compensation incorporated into their design to offset the mismatch in mask and wafer coefficients of thermal expansion (CTEs) that, at larger wafer diameters, aggravates the tendency for misalignment. As mentioned earlier, mask-to-wafer alignment is a manual process and is therefore somewhat rudimentary.


Figure 4. Die size reductions and effect on bump pitch.
Click here to enlarge image

Electroplate accommodates 300mm wafers quite well because photolithography eliminates CTE mismatch considerations. There is much work to be done, however, before the first electroplate-bumped 300mm wafer is produced. Attributes of bump height uniformity and composition across a wafer must be examined closely. Flow dynamics, cup design, and electrode design will be critical factors in controlling 300mm wafer electroplate.

Electroplating challenges

Although electroplate bumping offers many advantages over evaporation methods, it presents several challenges for initial implementation. The following are some of its more obvious problems.

Wafer contamination. Incoming wafers have exposed metal bond pads with a thin oxide layer on the surface, and an initial plasma pre-clean is performed to remove the oxidation layer. Additional contaminants that need to be removed to initiate successful bumping are often found on the wafer surface, however. Contamination on the passivation surface may not allow proper adhesion of the UBM to the passivation or may cause underfill delamination at the die surface during assembly. Additionally, any residue left in the vias because of an error in the wafer fabrication process or from improper removal of residual organic photoresist may cause improper plating or contaminate a plating bath.

UBM structure to work with all alloys. Electronic components are reflowed multiple times during the process of bumping, assembly, and final attach to the motherboard. During these multiple reflows, tin in the solder migrates to the UBM interface and forms intermetallics that provide a robust adhesion structure. Although tin plays this important role in forming intermetallics, if the thermal budget is exceeded, the tin can consume the UBM and lead to reliability failures. The specific UBM, bump alloy, and downstream thermal processing must be completely understood to maintain a reliable interconnect.

Uniformity. Size and coplanarity of the completed bumps are dependent on a number of factors, including mask via sizing, plating uniformity, flow characteristics, resist uniformity, and plating current density. The variance in plating and bump height uniformity may be plating's largest challenge. Solution flow patterns, cup design, contact clip methodology, and current densities within a plating system must be optimized to achieve ideal uniformity across a wafer and, more importantly, across the die. Current densities are highest near the cathodes and, in general, plating is proportional to the current density as long as the plating is not diffusion limited. This tends to cause higher current densities and therefore faster plating rates at the edge of the wafer as compared to the center.

Sputtered film etch. In the electroplate process, the UBM and seed metal materials are selectively etched from the wafer in the presence of solder. The primary concerns with this process are the undercut of the UBM structure and the oxidation of the solder because of the wet etch chemistries. Etch chemistries can preferentially attack the UBM structure and reduce the diameter of the UBM, diminishing the bump's mechanical integrity. Undercut can be affected by flow characteristics in the bath, location in a wafer boat, and etch chemistries. Tight process controls must be established to ensure that the proper etch attributes are achieved. Another important attribute of the etch process is the effect on the oxidation of the plated solder. The ability to successfully reflow bumps into their proper shape is compromised in cases where extreme oxidation occurs. This may cause non-wet problems during the process of joining the die to the component substrate.

Reliability. Bumps play a crucial role in component reliability. Evaporated C4 bumps have a long history of reliability on ceramic substrates; many companies have used C4 technology for producing millions of devices. On the other hand, electroplated bumps do not have the extensive field data to support their widespread acceptance. Companies deciding to implement electroplate bump technology will be required to provide sufficient data demonstrating reliability. UBM design, structure, and materials, and the bond pad under the bump are as important as the robustness of the solder bump itself. The UBM/bump structure cannot be disassociated from the polyimide, underfill, and substrate with which it interfaces. It is the careful and knowledgeable combination of these complex constituents that provides the key to acceptable reliability. As device and reliability requirements vary by market and application, some companies will find it easier to implement electroplated technology than will others.

Conclusion

Finding one wafer-level bumping process to accommodate all device and package roadmaps is a major objective. The flexibility of the electroplate bumping process has the potential to meet projected future needs. All major high-performance IC manufacturers either use or plan to use electroplating to service their advanced products. This process possesses the flexibility of depositing different solder and lead-free alloys, of producing bumps with very tight pitches, of using different metal films and sequences, and of obtaining heights and diameters customized to accommodate any product requirement.

Electroplate bumping also appears to be the best potential process for wafer-level bumping of next-generation 300mm wafers. Most bumping processes are capital intensive; a prudent philosophy is to employ a single high-volume, high-yielding bump process to achieve a cost-effective product. This high-volume process must be flexible enough to accommodate any product requirements without adding or omitting major capital equipment sets.

While the electroplate bumping process appears to be a good solution, there is still room for process improvements and equipment and process optimization. The process yield must be greater than 99% because the starting material is a completed IC. It is important to understand not only the cost of bumping, but the total system cost also. By making trade-offs when using concurrent engineering, a lower system cost may be achieved.

References

  1. E.M. Davis, W.E. Harding, R.S. Schwartz, J.J. Corning,”Solid Logic Technology: Versatile High Performance Microelectronics,” IBM Journal of Research and Development, p. 102, 1964.
  2. A.D. Aird, “Method of Manufacturing a Semiconductor Device Utilizing a Flexible Carrier,” US Patent 3,689,991, 1972.
  3. T. Kamei, M. Nakamura, “Hybrid IC Structures Using Solder Reflow Technology,” 28th Electronic Components Conference Proceedings, pp. 172-182, 1978.
  4. C.J. Speerschneider, J.M. Lee, “Solder Bump Reflow Tape Automated Bonding,” Proceedings 2nd ASM International Electronic Materials and Processing Congress, pp. 7-12, 1989.

For more information, contact John Franka, Motorola SPS, 3501 Ed Blue stein Blvd., Austin, TX 78721; ph 512/933-2148, fax 512/933-6981, e-mail [email protected].

David Clegg, Rebecca Cole, John Franka, Doug Mitchell, Dave Wontor, Motorola Semiconductor Products Sector, Austin, Texas

By Beat Mueller

In the past, most integrated circuit (IC) packages used wirebonding as the interconnect technology between chip and leadframe. Typically, several heavy wirebonds were used for power applications to give an appropriate connection for the higher currents (Figure 1). These heavy wirebonds have been increasingly replaced by clip (bridge) technology, whereby all of the heavy wires are replaced by one clip that connects the leadframe to the source of the chip.


Figure 1. Traditional interconnect examples for small-outline packages.
Click here to enlarge image

With the introduction of new interconnect technologies, companies have begun to produce devices on metal leadframes with flip chip interconnect technology instead of wirebond connections. Figure 2 shows an SO-6 package using flip chip connections for all inputs/outputs (I/Os). Each I/O has a solder ball and is directly bonded onto the appropriate leadframe. Figure 3 shows a micro leadframe package (MLP) (also called leadless plastic chip carrier [LPCC], quad flatpack no leads [QFN], micro leadframe [MLF], etc.) design. Such a design uses solder balls for all of the lead connections and heat dissipation requirements; additionally, the solder balls maintain the electrical properties of the ground plate through the middle metal pad.


Figure 2. SO-6 package.
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The sketches in Figures 2 and 3 are only a snapshot of the range of potential flip chip packaging solutions on metal leadframes. Other designs being considered are combinations of flip chip interconnect with clip/bridge attach technology to further improve the electrical and thermal properties of performance-driven applications. Clip/bridge attach technology was introduced a number of years ago and replaces several heavy wirebonds with a simple metal clip.

Technical Advantages

The advantages of a flip chip package design for small-outline (SO) devices come in the forms of electrical and thermal performance. In terms of thermal performance, the dissipation of heat is much better than when compared with a wirebonded device because of the large cross-section and good conductivity provided by the solder balls (Figure 4). Heat is conducted directly from the active side of the die through the metal leads and onto the printed circuit board (PCB). There is also heat dissipation through the back of the die to the plastic packaging. This allows higher currents with the same package size and design.


Figure 3. MLP package.
Click here to enlarge image

Electrical performance also is enhanced when wirebonds are replaced by solder balls, because solder balls have a lower resistance and can carry a higher current. This is especially important for die used in portable and battery-driven devices, where the package needs to be small and consume less power. Flip chip connected components have advantages when running at higher frequencies compared to their wirebonded counterparts. This is particularly important with the ever-increasing switching speeds of today's communication and processing components.

Cost Advantages

Using flip chip technology enables an engineer to pack larger die into the same package area compared with conventional wire bonded packaging (Figure 5). The space that is required for the wirebond on the leadframe and the epoxy bleed-out around the chip can then be used for a larger die size. This offers several opportunities for a package designer, such as adding more functions in the same device without needing to change the package type or size. This translates into cost savings in two ways: There are more functions in the same package, and using the same package means no changes and the same surface area on the PCB side.


Figure 4. Cross-section of SO package with flip chip interconnect.
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It is also possible to move a device from a large package into a smaller and cheaper one – for example, from a small-outline integrated circuit (SOIC) to a small-outline transistor (SOT). This saves packaging costs and gives the possibility of reducing the required footprint on the PCB. Additionally, the machine concept is flexible and can still be used for a traditional epoxy die attach process.

Flip Chip Connection Technologies

The industry uses a variety of interconnect technologies for flip chips. Some use solder balls or paste, while others use conductive epoxy to connect the bond pad on the chip to the metal leadframe. Figure 6 gives an overview of some interconnect designs used for flip chip, including eutectic solder ball, high melting solder ball with low melting solder paste, conductive epoxy without bumps, solder bump with conductive epoxy, and stud bump with conductive epoxy.


Figure 5. Size comparison of flip chip vs. wirebond.
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All of these methods have one thing in common: The processing equipment needs to have the capability to dispense very small and exact amounts of flux, solder paste or conductive epoxy (depending on the process) to achieve a reliable result and a high yield.

Flip Chip Die Attach

The key issues for a competitive flip chip on metal leadframe process are: integrated die attach equipment (including solder paste application and reflow oven), high units per hour (UPH) (to reduce the cost per produced device), and a small footprint achieved by a specially designed integrated reflow oven for leadframes.


Figure 6. Examples of different flip chip processes.
Click here to enlarge image

A fully integrated die attach and reflow platform (Figure 7) performs the following process steps inline without manual handling or interfacing among the individual steps:

  • unloading the leadframe from stack
  • dispensing small solder paste dots
  • die pick, flip and attach
  • inline reflow
  • unloading of leadframe into magazine.

Solder Paste Dispense


Figure 7. A proprietary integrated solution for flip chip assembly.
Click here to enlarge image

Because of a small bump pitch, it is necessary to dispense very small solder paste dots onto the leadframe. The dot diameter should be very small with the shape closely controlled and repeatable (Figure 8). Having already integrated the stencil print onto the die attach platform, a stencil printing step before die attach is not necessary, so this can reduce the overall investment for the whole flip chip line (Figure 9). It is also possible to apply solder paste dots onto bond pads that are lower than the leadframe surface.


Figure 8. Solder paste process for small dots.
Click here to enlarge image

The existing proprietary volumetric dispensing system had to be modified and is now able to apply solder paste onto the leadframe immediately before die attach, even for small bump pitches. It is important to use an appropriate solder paste of the proper quality and consistency to achieve the best results (Figure 10).

Flip Chip Die Attach


Figure 9. Process comparison – screen print vs. dispense.
Click here to enlarge image

The module for flip chip die attach is an enhanced bond head for normal chip attach with an integrated chip flipping unit. This module allows picking of the die from the wafer, turning the die face down and attaching it onto the leadframe without any loss of throughput. It also handles the chip gently so as not to damage the die surface, edges or bumps.

Integrated Inline Reflow Oven


Figure 10. Cross-section of bump to leadframe connection inside an SO package.
Click here to enlarge image

To avoid any displacement of the attached die before the reflowing process, it is necessary to keep handling between die attach and package reflow to a minimum. Today, bonded substrates are often put into a magazine and then manually transferred to a batch oven. The substrates are also transferred over a long inline track to a horizontal reflow oven. The use of this integrated system of an inline reflow oven that is directly attached to the die place machine enables substrate handling to be reduced to an absolute minimum.

High Throughput

With a unique bond head integrated flipping mechanism, it is possible to achieve a UPH of 2,500 to 3,000 for most flip chip on metal leadframe applications. This is important because SO packages are primarily used for low-cost devices where the cost per die attach is significant and has a major influence on the resulting total package price.

BEAT MUELLER, product manager for flip chip die bonding, can be contacted at Alphasem AG, Andhauserstrasse 64, CH-8572 Berg, Switzerland; +41-71-637 63 63; Fax: +41-71-637 63 64; E-mail: [email protected].

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Build-up substrates and next-generation design tools Contribute to the miniaturization of electronics.

BY KENT McLEROTH

As the electronic products industry continues to push the envelope of extreme miniaturization, product development teams are being forced further into the realm of high density interconnect. Design techniques and substrates labeled exotic only a few years ago are now considered mainstream. In particular, build-up substrate usage has grown dramatically, and is now found in a large percentage of high-production electronic products.

Build-up substrates saw their first large-scale usage in Japan's competitive consumer electronics market to meet the need for small, lightweight, high-performance products. Product markets for mobile telephones, notebook computers and digital camcorders have become so competitive that relatively small differences in size, performance, price and time-to-market routinely make the difference between a successful product line and one that fails. For this reason, new technologies, such as build-up substrates and next-generation design tools, are needed within these competitive markets.


Figure 1. Representation of a substrate, illustrating core layers, build-up layers and allowable via types.
Click here to enlarge image

The proliferation of build-up has caused design teams to rethink both their design approach and the software tools used to accomplish these designs. This article is intended to help electronic design teams move from traditional substrates and design techniques into incorporating the latest technological advances in high density interconnect.

What is Build-up?

Build-up substrates are now available from a wide variety of vendors, encompassing many configurations. There are, however, several attributes that are common among build-up types, including:

  • Size reduction (lower substrate size, weight and volume)
  • Increased wiring density, including closer component spacing and smaller component footprint
  • Higher densities, which translate to lower cost per connection
  • Improved electrical performance, including a tenfold reduction in parasitics from through-hole designs
  • Lower RFI/EMI (ground planes can be closer to, or on the surface, and distributed capacitance is enhanced)
  • Greater design efficiency (microvias allow for easier part placement on both sides of the board, and “via in pad” allows for easier escape routing and higher densities).

EDA Tool Requirements


Figure 2. Example of a staggered via. Note the size of the core via in relation to the conformal (micro) vias and the distances maintained between.
Click here to enlarge image

Successfully designing for build-up requires an electronic design automation (EDA) tool that supports the unique rules and requirements necessary for these substrates. The most fundamental of these requirements is the ability of the tool to accept and support build-up layer structures. In many cases, materials vary among layers requiring layer-specific and layer-to-layer specific rules. In addition, multiple via structures must be supported within a single design technology. Typically, these may include conformal (micro) vias, inner conformal vias, skipped (landless) vias, through-core vias and through vias (Figure 1).

An EDA tool should have parameters in place to support these via types, and use them in the correct design situation. Each substrate configuration requires specific rules for each via type. Most manufacturing methods limit the via combinations that can be used and minimum distances between them, requiring techniques, such as staggered, spiraled and stepped vias (Figure 2).


Figure 3. Build-up specific rules, including center-to-center via pitch, must be supported by the EDA tool.
Click here to enlarge image

Build-up design requires that additional rules, not required by traditional substrates, be supported. Without such build-up specific rules, an engineer runs the risk of designing a product that cannot be manufactured. Selecting an EDA tool intended for design on build-up substrates is a requirement for designing accurately and efficiently.

One example of a build-up specific rule is center-to-center via pitch (Figure 3). Center-to-center via pitch is required to ensure that the via configuration is correct through the entire substrate. Once the basic layer and via conventions are defined, the tool must support, by layer, all of the necessary clearances required by the substrate materials. This includes clearances for each via type individually (Figure 4). An EDA tool should support these individual clearances to take full advantage of the characteristics of the substrate.


Figure 4. Clearance rules defined individually for each via type.
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Additional rules that must be supported include trace spacing by layer, landless via and through-hole clearances, component pad and resist clearances, substrate edge by layer, and standard PCB rule requirements.

Build-up technologies can provide dramatic space savings in the routing area, so routing functions should be able to maximize the opportunity. Microvias free up space that would otherwise be used by the larger through-hole vias, so EDA tools should exploit these advantages wherever possible. Intelligent “search via” capabilities allow staggered via patterns to avoid obstacles up through the substrate, assisting in providing the highest possible routing density. In many cases, “meshed” planes are required to enhance both fabrication yield and EMI performance (Figure 5). An EDA tool should have the ability to mesh solid planes in a variety of patterns.

It is also helpful if an EDA tool provides a user interface that allows the engineer to work in a three-dimensional environment. As substrate stackups become increasingly complex, it is more difficult to work effectively in a traditional two-dimensional environment.


Figure 5. Meshed plane.
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Figure 6, a traditional top-down view through the substrate, is acceptable when designing for a standard substrate. When designing for build-up, however, it becomes difficult to discern how the various vias are structured through the layers. Figure 7 illustrates a clearer view of the picture by providing the three-dimensional design environment.

Technology Partnerships

There are now several fabricators offering build-up substrates, each with their own unique set of advantages and design rule requirements. These requirements are changing as rapidly as the electronic products they support. It is therefore no longer practical for a design engineer to stay abreast of every substrate technology and the corresponding design rule requirements. This gap in technology awareness has spawned new relationships between EDA software providers and substrate manufacturers to deliver vendor-approved design technology kits to the market.

Such kits contain vendor-specific design rules, etch requirements, layer stackups, material information and via structures in a format understandable by the design tool. They are now available from a number of leading substrate vendors for the design engineering community.

There are advantages of using a vendor-approved design rule kit. Primarily, an engineer is assured of designing a product that can be manufactured. Rather than taking the time to thoroughly research all of the rules and requirements of a given substrate, an engineer may simply plug the appropriate technology kit into the EDA tool and begin the design. The kits, which are approved by both the EDA vendor and the substrate manufacturer, ensure the design will meet the manufacturing rules.


Figure 7. 3-D view of via patterns reveals a clear picture of the routing strategy.
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For instance, designs begin by selecting the appropriate substrate. Each substrate type has its own advantages with regard to size, weight,

density, circuit performance and cost. Once selected, an engineer can browse the library of substrate technologies. The appropriate technology kit may then be selected and plugged into a graphical technology viewer/editor for review. These editors are significantly more effective than the traditional text-based “rule matrix,” as they provide a clear picture of the technology requirements.

Once the technology and rule information has been reviewed in the technology editor, the information may be extracted into a format understandable by the EDA tool. Traditionally, rule files, layer creation, layer mapping, pad and padstack creation have been separate, manual efforts within the EDA tool. The graphical technology editor can perform all of these tasks in one step, ensuring that the technology and rules considerations specified by the substrate manufacturer are met by the design.

Summary

It cannot be reasonably expected that a design tool intended for traditional substrates can be used effectively to design for build-up technology. Designing for build-up using a traditional printed circuit board design tool can be akin to using a screwdriver to drive a nail. To complete the task efficiently, the proper tool should be selected. Items to look for in a build-up design tool include:

  • Support for build-up specific features, including layer stackups, micro vias, build-up via combinations, and mesh planes
  • Support for build-up specific rules, including layer-to-layer clearances and center-to-center via type distances
  • Graphical technology editor
  • Partnerships between the EDA vendor and substrate manufacturers.

The advent of next-generation EDA tools and technology partnerships removes much of the uncertainty of high density interconnect design, allowing design teams to take full advantage of leading-edge technology.

KENT McLEROTH, technical marketing manager, can be contacted at Zuken Inc., 238 Littleton Road, Suite 100, Westford, MA 01886; 978-692-4900; Fax: 978-692-4725; E-mail: [email protected].

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