Addressing industrial issues is key
BY JACKY SEILLER
Bumping technology has reached the point where it can be a cost-effective packaging alternative for advanced high-volume applications. At the same time, it should be recognized that the industry has a learning curve to overcome, and bumping technology must be used cautiously if it is to develop to its full potential.
Dice suppliers must carefully consider a wide range of alternatives at nearly every step of the bumping process. What bumping technology is best for the application? At what stage in the manufacturing process should bumping be carried out? When and how should testing and inspection be built into the overall process? Only if these and other important questions are asked – and answered – can bumping be successful.
Bumping Options
Ramping up for delivery of bumped bare die can be a daunting task for manufacturers. Satisfying the end-user, of course, remains the bottom line, and customers are asking for increased miniaturization and integration of the flip chip concept into advanced projects like multi-chip modules, fine-pitch liquid crystal display (LCD) drivers and even system on chip (SOC). Beyond considering basic issues, such as design, process flow, wafer testing, inspection and quality assurance, bumped bare die suppliers must choose from various technical alternatives before investing in an in-house process.
 Figure 1. Bumping technology alternatives. |
There are different configurations to evaluate and choose from and the chosen alternative must be integrated into a well-optimized process flow. The end-user can select bumped bare die deliveries that will be flipped directly onto application boards (Figure 1a). Or, bare die may be mounted in a flip chip ball grid array (BGA) package before testing (Figure 1b). Finally, there is the direct-chip-attachment (DCA) alternative, in which bare die are attached to a substrate with embedded passive components (Figure 1c), the whole module being mounted on the printed circuit board (PCB).
A Closer Look
There are five basic types of bumping processes in use today:
solder stencil printing (Figure 2), solder screen printing (Figure 3), solder or gold electrolytic deposition (Figure 4), gold stud bumping and sputtering. All are wafer-level operations in which wafers are bumped after the conclusion of the wafer fabrication process. Each has its own degree of maturity and each has specific characteristics that must be considered in selecting the right process. In each case, a supplier must choose between subcontracting and taking the bumping process in-house. Subcontracting, of course, assumes that an outside vendor has both the capability and the capacity to handle the process in the volume required by the end-user at the right cost.
 Figure 2. Solder stencil printing process during solder paste deposition. |
One key factor in choosing the best bumping technology is the application board or PCB itself because its minimum design rules must be compatible with the defined bumping pitch of the process. For example, suppose an LCD driver has a silicon pad pitch of 60 to 70 microns. Solder bump technology cannot be used because the required pitch is too small, so generally anisotropic conductive film (ACF), along with electrolytic gold bumping, becomes the preferred approach. In this case, the substrate is glass and the substrate pitch is compatible with the minimum pitch of gold bumping technology.
On the other hand, for high pin count die, pads may be staggered on two or more rows or columns, or even located in a full array matrix. In that case, the technology of the board must be carefully chosen to provide an escape route from the central bumps. The space between traces, trace width and the via technology used must make it possible to route even the central bumps.
 Figure 3. Solder screen printing process during solder paste deposition. |
Gold electrolytic bumping is one process that is widely available and used extensively. The applications are numerous (chip-on-glass LCD drivers, tape automated bonding, watch industry, plasma display drivers, etc.), and this technology has been well-stabilized for some time. Gold electrolytic bumping sources for 6-inch wafers are available in Europe, the U.S. and Asia. However, only a few 8-inch wafer production lines are compatible with this technology.
Today, demand for bumping is increasing rapidly. Still, the decision to invest in an internal bumping line comes after considering the process, the needs of the customer and the demands of the technology. Other issues to consider are yield, throughput, minimum pitch, redistribution option availability, compatibility with different alloys (including lead-free alternatives), the use of toxic chemicals, waste disposal and cost.
 Figure 4. Solder electroplating process after solder or gold electrolytic deposition. |
When bumping is outsourced, multi-sourcing concerns become important. It is not always easy to find two compatible sources of bumping. This is primarily because standards for production infrastructure are not yet universally established in this domain. In fact, actual demand for solder bumped devices is still more for engineering quantities than for production volumes. A notable exception is for applications that are incompatible with wire bonding technologies because of small pitch requirements or radio frequency (RF) constraints, such as inductance because of wires and high pin count.
It is often more cost-effective to solder bump an existing die rather than fully redesign it, matching the new design with bumping design rules. Lead-time to get evaluation samples is much smaller and it eliminates the need to build a new set of masks and to launch a specific diffusion lot dedicated to bumping. However, if a device originally designed for wire bonding has pad location and pitch parameters that are incompatible with solder bumping design rules, it may be necessary to fully redesign the die. Another alternative is using a redistribution layer (RDL) when possible.
RDL Pros and Cons
RDLs are formed by adding passivation and metal layers on the top of the die, relocating the pads according to the design rules of the solder bumping process (Figure 5). This additional step, done as an optional part of the bumping process, can shorten cycle time and speed delivery of engineering samples. The downside is that it can impact device reliability and electrical performance if bumps are positioned over the active area. Also, it is generally quite expensive, increasing the cost of the bumping process by up to 50 percent.
 Figure 5. Redistributed bumped die. |
The design rules generally recommended today include a peripheral pitch of 200 microns and an array pitch of 250 microns. For most solder bumping technologies, the short-term peripheral and array pitch roadmaps are l30 microns and 180 microns, respectively. For volume production of small-pitch devices, it is usually best to directly design or redesign the die according to these proven rules instead of using an RDL. That supposes that input/output (I/O) libraries have been developed and qualified, that bumping on active areas has been qualified, and that design rules of the application PCB on which the die will be flipped are compatible with the pitch on the die.
Bringing out signals from the center of a die with high numbers of I/O pins is not easy in a full array matrix of bumps. This problem can be fixed with a PCB technology having more layers or using a more aggressive design, in terms of pitches, via sizes and trace/spacing dimensions. Mainly because of the high cost of the PCB technology used by the final customer for routing, the global production cost is generally much higher for small-pitch PCB technology.
Another design-related constraint is the current density capability (A/cm2) of the bump materials. It is wise to be conservative in this area. For example, the maximum current density for eutectic SnPb solder is about 4200A/cm2. Electromigration can start at that point, depending on environmental conditions, such as junction temperature. Maximum recommended current is generally in the range of 50 to 300mA, depending on other factors like passivation opening, junction temperature, UBM (under-bump metallization) diameter and material. The redistribution layer can also become a current bottleneck.
Lead-free Alternatives
Solder bumping typically uses lead-based alloys (Eutectic 63/37 SnPb, 10Sn/90Pb or 5Sn/95Pb). There is a growing trend toward the use of lead-free materials. The principal alloys in use are 96.5 Sn-3.5 Ag and 95.5 Sn-4.0 Cu-0. 5 Ag. Melting temperatures are approximately 220 to 230°C, which requires a reflow temperature of 250°C.1 Temperatures can be even higher for other lead-free alloys based on Bi and Sb. This imposes a serious constraint for use with organic substrates. The lead-free alloys considered for flip chip processes must be compatible with the assembly of the other components on the application boards with respect to temperature, flux, multiple reflow, pastes and cleaning processes. The reliability of lead-free alloys must also be compatible with a wide array of applications, ranging from low-end to high-end products and markets ranging from consumer to automotive.
The process of characterizing potential lead-free alloys is not yet well established and a good deal of investigation is still under way. The impact on costs can also be significant and should be carefully evaluated. Finally, multiple sourcing of lead-free solutions is difficult. Actually, ternary alloys seem to be more suitable for bumping processes, like stencil printing or screen printing, as it would be difficult to control the stability of the composition during electroplating. Several international groups are very active in this field and the move to lead-free materials will probably gain momentum over the next few years.
Process Flow Constraints
When bumping is integrated into a volume production operation, the process flow has to be planned carefully to avoid dramatic increases in costs and cycle time, as well as reduced yield. The usual flow before integrating the bumping step consists of wafer fabrication, thickness reduction, electrical wafer sort and shipment to assembly. The bumping operation can be integrated after wafer fab, thickness reduction or electrical wafer sort.
 Figure 6. Standard epoxy probing mark. |
Because bumping process yields are affected by wafer thickness, reducing wafer thickness before bumping has drawbacks. The impact of this limitation can be significant. For example, in portable applications, the thickness of the final assembly is a key factor and the wafer thickness after a standard thickness reduction process is typically about 375 microns for 8-inch wafers. This is usually not compatible with the bumping process, which requires a minimum thickness of approximately 550 microns if yield is to remain in an acceptable window. In that case, it may be necessary to reduce wafer thickness after solder bumping. Bumped wafer handling – shipment, mounting, sawing and flip chip processing – becomes more critical on thin wafers. Finally, thickness reduction of solder-bumped wafers is more expensive, partly because of the materials used during processing, but also because throughput is reduced compared to unbumped wafers.
If only bumping is subcontracted, positioning the bumping step just after wafer fab means that wafers must be shipped to an outside supplier and then returned for wafer thickness reduction. During this operation, the bumps must be protected either by a dedicated sticky foil on the front side or by a resist to be removed chemically after completion. Then, the front side of the wafer must be cleaned using plasma or chemical processing. This is needed to ensure that residues will not affect the adhesion of the underfill after flip chip attach, and to avoid any impact of potential residues on reliability.
Bumping after electrical wafer sort (EWS) has an advantage over other alternatives. It is not easy to electrically test bumped wafers because the soft bump materials can stick on the extremity of the probe. This can reduce EWS throughput because of the frequent cleaning that must be done on probes. Of course, EWS before bumping assumes that the bumping process is compatible with probing marks in the pads. Only a few processes allow such marks before bumping. It is necessary to map the wafers electronically and make sure the electronic mapping format is compatible with the wafer inspection system to be used after bumping.
 Figure 7. Vertical probing. |
Performing bumping before EWS eliminates concerns about bumping on probe-marked pads. Bumping before EWS, however, requires that flip chip equipment be able to track good die using electronic mapping. Almost all die attach equipment, including flip chip bonders, can do this. A final caveat is that any impact that the bumping process has on the electrical integrity of die cannot be detected if bumping is done after testing.
Testing Alternatives
Electrical testing on bumped wafers is, of course, a critical part of the bumping process. In the case of peripheral solder bumps and even a two-row staggered structure, a standard probing card configuration can be used. The probe design, including shape and material, can be optimized to minimize the downtime of probers and probe cleaning frequency. In the case of an array of more than two rows, vertical probing card technology is needed to access bumps located in the center of the die. Vertical probing largely eliminates the problem of material sticking on probes (Figures 6 and 7). On the other hand, the wiring needed for vertical probing limits testing frequency to not more than a few hundred megahertz.
Before choosing the testing technology, prober parameters, such as offset, speed, probe cleaning frequency and testing temperature range, should be considered. At high temperatures, solder alloys can soften, resulting in bump deformation. In addition, the cost of a vertical probing card is much higher than the cost of standard epoxy probing cards – up to 10 times higher depending on factors like configuration, pin count, supplier and production volumes. In the case of RF bumped die that must be flip chip attached in a package and tested internally at high frequency before shipment, the test can be done after packaging. Prober offset can also be set to electrically detect missing bumps.
The bumping process introduces defects that are often detected by a visual inspection of wafers. Full 100-percent optical inspection is expensive and can only be used if the cost of such an operation is in line with the cost target of the application or if the customer requires it. For volume production, inspection can be automated, making the use of statistical process control (SPC) possible. Computerized results are both less costly and more reliable. So far, SPC is in use by only a few bumping service suppliers and many aspects of this approach are still being investigated.
Physical Measurements and Inspection Methods
Bumps must be measured to confirm that bump height is within specifications and to verify coplanarity of bumps within a single die. This is essential to ensure that bumps are sufficiently coplanar to be compatible with the next steps of the flip chip process, including fluxing and contact with traces. This is especially important for gold bumps, which are much smaller than solder bumps and, therefore, more sensitive to bad coplanarity in such cases as flip chip in ACF.
A 100-percent measurement operation can be time consuming; in one case requiring several hours to measure 40,000 solder bumps on a single wafer. That makes a low-rate sampling approach a good compromise in terms of risk and time for this type of quality assurance (QA). Fortunately, bumping processes are generally sufficiently consistent with respect to height and diameter so that 100-percent measurement is not necessary. A few bumps measured on carefully chosen locations within the wafer should be enough. For bumping technology characterization, it is necessary to determine the range of bump height variations within a wafer, which depends on the bumping process type. For example, electroplating processes provide systematically smaller bumps at the center of the wafer, compared to the edges, because of the electrical resistance of the seed layer used to polarize the bump sites.
X-ray control is a good way to make sure that bumps are relatively void-free and that the voids are within specification. Today, void-free bumping processes do not exist and the commonly agreed specification is an X-ray-verified void diameter that is no more than 30 percent of bump diameter. This specification has limited utility because, after reflow, bump diameter is no longer a reference. The appropriate parameter is either the UBM size or the passivation opening. Because this void specification issue is still an open question, it is mandatory to have X-ray equipment able to detect voids as small as 10 microns. In addition, all equipment dedicated to controls or visual inspections must be compatible with wafer mapping.
Bumping Process Qualification
Qualification of a bumped product can be done in several different ways. The bumps themselves can be qualified independent of the application, with the customer taking care of the qualification of the final flip chipped product. In this case, the bumping qualification will be focused on bumping process as well as on bump structure and evolution of the structure (intermetallic layer, for example), shear tests vs. temperature cycles, and aging.
Bumps can be qualified directly on the application, if necessary. Impact of stress because of the application itself (substrate material, underfill) can only be measured for qualification purpose after the flip chip process. On the other hand, it doesn't make sense to qualify bumps independently of the application board, because those tests are often dependent on temperature variations and thermal expansion. The reliability of a flip chip connection depends on the temperature range of the application, bump material and structure, bumping and flip chip processes as well as materials, such as flux, underfill and substrate.
The global yield and reliability of any application also depends on the number of devices, both silicon die and passive components, mounted on the application. The final customer often requests a quality assessment, sometimes including reliability tests at die level. The decision to develop such a process is strongly dependent on its impact on the global cost of the application. That, in turn, is linked to factors like complexity, number of devices integrated in the application and market segment. The approach will be different for an application on which only one small die is flipped on a low-cost single layer board, compared to a flip chip multi-chip module on which passive components are mounted and integrated in a very complex and high-density PCB.
Failure analysis isn't easy, as the die is flipped and often sealed in underfill material or molding compound. One method uses non-destructive methods employing analysis tools like X-rays to allow checking several points while maintaining the integrity of the assembly. There is no chemical or mechanical failure analysis process that can make further analysis easy. Sonic acoustic microscopy can help, but today's transducers have insufficient resolution and sensitivity to reliably detect voids or bridges through silicon and assembly materials (substrate, underfill). Furthermore, resolution is still not good enough to accurately detect delamination at the UBM interface.
Destructive analysis involving removal of materials with chemicals, plasma or mechanical processes sometimes
provides some interesting information, but often makes interpretation more difficult due to residues, uncontrolled material etchings, and other such parasitic effects. Both destructive and non-destructive methods can be used advantageously. How this should be done depends on target cost and on the market segment of the end product.
AP
Reference
- J.H. Lau and Y.H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip and Fine Pitch SMT Assemblies, McGraw Hill, 1997.
JACKY SEILLER, process and specific projects manager for back-end and assembly engineering, can be contacted at STMicroelectronics, 12, rue Jules Horowitz, BP 217, F-38019 Grenoble Cedex, France; +33 476 58 50 55; Fax: +33 476 58 55 29; E-mail: [email protected].