Automation wizards conquer package design


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Packaging no longer is an afterthought – it has moved into the mainstream, directly in the critical path of product design. Focusing on packaging at the last minute can cost a company up to 40 percent in performance, but fortunately software tools can help expedite package design. Such tools are aimed not only at contract package manufacturers, who remain the primary model for packaging design, but at semiconductor designers and manufacturers and systems companies, as well.

Because electrical packaging metrics have changed so much, many companies are bringing design in-house. When this is done, engineers and designers must balance the multiple domains of physical layout, electrical characteristics, thermal performance, manufacturability and test. They need to look beyond the package and explore the interactions between the adjacent levels of chip interconnect and printed circuit board. Additionally, they must learn to use more sophisticated tools.

Contemporary software tools can enable fast evaluation of design alternatives while adhering to physical and electrical constraints. Early ball grid array (BGA) and chip scale package (CSP) designs were attempted on legacy mechanical systems employing add-on electrical macros; this resulted in a slow and costly design cycle because of undetected connectivity and assembly errors.

Those who traditionally have not involved themselves in direct packaging design can turn to new tools that allow package design to proceed concurrently with chip design, once the size and number of I/Os have been roughly determined. At that point, designers can perform a feasibility study to explore package options, get a feel for the geometries involved and required substrate material, perform a quick electrical analysis and so on. At the end of a study, the design team should have a good idea of how a particular package will impact a device's overall performance.

So How Is This Done?

The first task designers face when using advanced packaging software involves transferring die data into the package design. Information about the X-Y locations of the pads and the die size and shape usually resides in a GDSII or ASCII pad table file. This forms the input to the tool, which must be prepared to accept the required file size and format. Before a chip design has been completed, preliminary package designs can be laid out manually by filling in parameters on templates, and the tool constructs the preliminary die design.

Thus, an advanced software tool should offer three ways to construct a die part: by importing ASCII text or GDSII files, or by parametric construction. In essence, once a GDSII file is read, its contents can be displayed in a preview window, with the cells and layers comprising the file presented in a list to browse and select. Users should be able to set additional filters to ignore extraneous shape data and enable the die-specific information to be extracted.

Figure 1. Increasing chip complexities.
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Software systems also allow users to create a bond shell, or wire-bond pattern (sometimes also referred to as a dispersion or fan-out pattern), for the wires to be placed from the top of the die to the substrate. Designers can judge package sizing and balance, or possible inductance or other problems against wire placement and sizes. For example, suppose the first iteration produces an arrangement in which all bonds fall into a single concentric ring around the die. This may be a fine solution, unless the resulting wire lengths are so long that they produce an unacceptably high inductive coupling.

On-going “what-if” exercises may result in two or three concentric rings, where the wire bonds are staggered to stay within maximum wiring sizes. With advanced simulation tools and wire-bond wizards that automatically generate patterns based on user-defined design constraints, designers can run through such scenarios, almost in real time. At the same time, they can incorporate and weigh off a myriad of other requirements – routing, manufacturing and electrical performance.

In the search for the right package, other questions can be answered by using software: Will there be any netlist problems at the package or, more important, at the board level? Will the inductances meet required margins? If problems are encountered, package designers can ask the chip designers to, for example, swap around specific gate or I/O assignments to eliminate electrical or board-level problems even before the chip's design has been completed.

Handling Interconnect Routing

Routing interconnects from the substrate bond pads to the ball pads on the package is a major task. Although much of the early automatic routing technology is still viable today, the routing challenge is often more complex than can be met by the directional nature of traditional autorouters.

Automatic routing of packages requires technology that is capable of routing at any angle on a given layer – that is, a suite of non-directional algorithms capable of producing dense, all-angle routing for advanced package designs. Because some designs are so dense, even an autorouter cannot achieve 100-percent completion. An interactive editor can operate under the control and guidance of continuous design-rule checking, so users won't be able to enter a violation or go back in upon completion to check on feature sizes or clearances.

So designers need different options to use. For instance, they may call up a signal integrity tool to see whether there are any switching or crosstalk problems. Or they may want to know whether the bond wire inductances are too high.

Die Flags and Power Rings

Once the signal I/Os have been routed, the crucial power and ground connections (otherwise called the die flag and power rings) must be considered. Most single and some few-chip packages require metal areas and rings under and around the die. The multi-spoked metal area under the die is commonly referred to as a die flag and is typically connected to ground. Additionally, die flags act as a heat sink and provide a thermal pathway for heat dissipation. The shape of the die flag varies with the particular design and is determined by electrical, thermal and stress analyses.

Surrounding the die flag may be several concentric rings, called power rings, that serve as common bonding points for the power connections to the die. Usually, there is one ring for each voltage, so the number of rings needed depends on the number of voltage levels.

Until recently, users had to painstakingly construct the die flag and rings manually using design copper shapes or import the shapes for an AutoCAD DXF file. With automation, users can select a die part in a layout editor, launch a wizard and let the software complete the process. To save time and streamline the design process, parameters are included that define the soldermask openings for the die flag and rings. A tool can use these parameters to automatically construct the die flag and rings on assigned layers using design copper shapes. Once created, the shapes can be further modified using standard editing functions.

Automated Package Design

In short, new automation software can assist with time-intensive tasks, such as wire bonding or trace routing. Intuitive, easy-to-use dialog boxes and wizards that appear in a logical progression can do the laborious work, and engineers and designers can focus on design specifics. Besides the tools available for package design and feasibility studies, those for signal integrity analyses and fabrication optimization have become indispensable. In the end, software can only help in planning, identifying areas prone to fabrication problems and improving substrate yield. The new tools are intuitive and their features can be put to work right out of the box.

Jim Martens, manager of the interconnect solutions group, can be contacted at Innoveda Inc., 293 Boston Post Road West, Marlboro, MA 01752-4615; 508-357-8144; Fax: 508-303-5595; E-mail: [email protected].


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