Chip/package co-design

The bridge between chips and systems


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Because of deep sub-micron technology, chips now contain more functionality and are being driven to higher performance levels than ever before. At the same time, manufacturing technology is undergoing rapid change, and mixed analog/digital logic can now be placed on the same die. With more functionality on the chip, designers have to cope with higher I/O densities, more signals coming out of a chip and tighter geometries. These higher performance requirements also have a significant impact on signal integrity. Issues such as simultaneous switching noise, crosstalk and resonance present increasing challenges to the design community.

Under these circumstances, the ability to design the chip, the package and the surrounding system concurrently becomes a primary advantage. Today, the influence of the package on system performance must be understood and analyzed early in the design cycle. Concurrent package design is becoming an important bridge between the design of a high-performance chip and its associated printed circuit board (Figure 1).

To optimize this concurrent IC, package, and system design strategy, a single interactive database is essential so that design teams can perform high-speed interconnect analysis – both physical and electrical – and make optimization trade-offs at all levels.

Concurrent Design Methodology

The overall blueprint for a new methodology for the concurrent design of chips, packages and systems is shown in Figure 2. The first column describes the requirements from the perspective of the IC designer, who needs to determine the target die size, the I/O floor plan and the I/O buffer requirements. To determine these requirements accurately, the designer must understand impact of the package on performance, and this knowledge needs to come through various interactions between the die and the package.

Figure 1. Package design is an essential bridge between IC and PCB design to make complex chips work effectively in high-speed systems.
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For instance, the die size must be based on physical feasibility studies. Physical feasibility indicates form and fit, which is determined by a variety of parameters, such as wire lengths or distance to power and ground rings in a wirebonded design. Likewise, form and fit for cavity designs is determined by whether the die fit in the cavity, and for chip scale packages by whether the die is larger than the package.

The I/O layout matrix itself should be determined by running a route feasibility analysis. This analysis determines the complexity of the escape pattern and establishes I/O assignments for a known good die/package. Once the assignment table is defined, electrical feasibility studies are performed on the entire chip/package interconnect. Assignment trade-offs and differential pair opportunities then can be determined using actual design data. Out of this interactive process, an initial I/O floor plan can be established for the chip designers. In addition, a package template is generated, from which the final package layout will be determined.

Figure 2. Interactions required for concurrent design of the chip, the package, and the PCB. A true IC/package/PCB co-design solution can be realized when tools share a common database and common analysis engines.
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Concurrently, the PCB designers try to determine what impact the PCB will have on the overall system performance. In the PCB world, designers experience problems being able to escape-route the large BGA components that are now coming onto the scene, and they need to understand the interconnect feasibility as well as the IC designer does.

Timing margins are another concern. These margins are based on the placement of components on the PCB, and PCB designers need to be able to feed that information back to the package and IC designers. The same is true of signal performance prediction – the extent and accuracy of the predictions are important.

Emergence of the System-level Package (SLP)

As the push toward systems-on-chips (SOCs) and deep sub-micron technology continues, the industry trend is toward more complex, high-density packaging. System-level packages (SLPs) are gaining acceptance as a viable alternative to SOCs as the industry begins to face the challenge of integrating multiple technologies onto a single chip. With the SLP approach, one or more ICs, along with other discrete components, can be integrated into a single high-performance compact package, which also may include both digital and radio frequency (RF) logic.

An SLP design methodology must have the capability to support both high-speed digital and RF circuitry in a single, multi-chip package. This methodology must address such issues as optimized I/O placement at the chip level for both flip-chip and wirebond interconnection, route feasibility analysis, and circuit simulation of the entire interconnect, from I/O buffers through to the printed circuit board.

Package Design Flows

Different types of design require different design flows. For example, the flow required for an RF circuit is different from that of a purely digital design. Each type of design flow requires a different set of tools, and any comprehensive solution must also have the flexibility for users to easily define their own flows and incorporate third-party point tools.

Figure 3. An ideal RF IC and package design flow.
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Figure 3 is an example of an ideal flow for RF IC and package design. Note that the package is being designed simultaneously with the IC layout process, and the design team is able to add passive components either at the package level or at the chip level. This flow promotes the ability to perform tradeoffs within each environment, and provides access to RF simulation tools to analyze these tradeoffs.

After design entry, the netlist and passive components are passed to the package designer along with a bare-bones die footprint. After the package layout process has been started, the existing package information is passed back to the IC designer for RF verification. The package layout process generates interconnect models that represent what the actual circuit will look like on the package, and RF verification is performed iteratively on both the chip and its packaging. Both 2-D and 3-D models are generated in SPICE and other formats to support a variety of popular RF verification tools.

Figure 4. An ideal digital IC and package design flow.
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The ideal digital design flow is a bit different, as shown in Figure 4. During the product concept phase, the digital IC designer who is responsible for I/O floor planning has only an estimated number of I/Os and a set of performance requirements. This designer starts a chip I/O planning process to determine how large the die will be. Details that need attention include the number of power and ground nets that fit on the chip, the wire-bond pattern for wire-bonded chips, and the escape patterns and power delivery for flip-chip ICs.

All of these things are decided in the chip I/O planning phase, and this information is then fed to the IC layout process. At the same time that the initial floor plan is fed into the IC layout tools, information about the package I/O assignments is also passed to the system design team to determine the impact on the system-level performance and the board layout. This flow also creates a “package template” containing information needed for the package designer to start the package layout.

At this point, enough information is available to perform a first-order analysis of the entire interconnect – from the I/O buffer to the PCB termination. This analysis phase not only determines the impact of the design on critical nets, but it also provides timing information that can be used to define the design constraints. In addition, it helps to avoid the problem of over-constraining the nets, which happens when there is insufficient information about how signals will actually perform in the final design. Over-constrained nets can result in designs that are impossible to route, added cost and longer design cycles. If the signal integrity engineers can be provided with more accurate models, then they can make more informed judgments as to what nets need to be constrained and at what level.

Figure 5. An ideal system-level package (SLP) design flow.
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Figure 5 shows a design flow for developing a system-level package that contains mixed RF and digital circuitry. The product concept, design entry, IC layout and RF verification processes are as seen in Figure 4, with the addition of an RF component modeler.

Feasibility Analysis

Chip I/O planning facilitates the design of ICs in the context of their packages, with bi-directional data and rules exchange between the IC tools and the packaging tools. Currently, in the IC space, there is only one set of rules that is based on the target manufacturing technology and its design constraints. However, there is a completely different set of rules in the packaging world. The new methodology must be able to incorporate those rules, so that as modifications are made in either the IC floor plan or the package, the effects are propagated to the other levels of design.

At this point in the flow, there is now real physical geometry from which to extract accurate modeling results, and the package can be modeled along with the chip. Thus, the designers are able to do simultaneous simulations of the entire packaged chip, instead of the chip designers just modeling up to the edge of the chip, without really knowing what will happen when the chip is in a package. This additional data can be incorporated into the models, even to the point where estimated printed circuit board models can be included as well.

In the physical analysis space, the new solutions have a built-in route feasibility phase so that designers can analyze factors such as wire bonds, escape routing, power and ground rings, and layer stack-ups. If a chip already has I/O assignments, the designer can determine quickly if the design is routable and how many layers it will require. If no assignments have been made, an automatic assignment algorithm based on route feasibility can be used to derive a known good assignment table with which to begin the design.

This design flow incorporates many two-way communication mechanisms. If changes are made – some pads are moved around or some I/O buffers are swapped, for example – that data must be back-annotated into the chip design tools.

Defining Design Constraints

After performing chip I/O planning, designers can begin to set design constraints at any level – chip, package or board. In theory, if a design meets those constraints, an optimally performing system is assured.

Two types of users are envisioned here. The first is the IC designer who wants to do some kind of estimates of the packaging and does not necessarily have a full design to work with. This designer may just want to get some ideas regarding physical factors, such as the die size range, escape routing and bond feasibility. From an electrical perspective, once the substrate cross-section has been defined, the parasitic information can be extracted from the package design. The geometry, including the material properties of the cross-section, can be extracted and models are then generated. Armed with these models, an IC designer is able to perform various types of analysis. A designer is then able to identify certain constraints that may need to be passed on to the package and the PCB designs. One of the key analysis steps is to check the power delivery system.

A package designer, on the other hand, certainly looks at some of the same issues, but might also decide to develop a series of package libraries so that an IC designer can reuse a previously designed packaging scheme. Package designers might want to develop a whole library of packages with different sets of stack-ups. From an electrical perspective, a package designer can also create libraries of ideal differential pair assignments for use by an IC designer.

Motivation for Custom Packages

For high-performance devices, once the critical nets get onto the package, many detrimental effects can result. Typically, there are crosstalk problems, reflection issues, impedance values that need to be maintained, and differential pairs that have to be accounted for. One of the most important things a designer derives from chip I/O planning is whether power and ground planes are needed within the package to meet power delivery requirements. From a cost perspective, this is critical, because if power and ground planes are used, it can double the cost of a package. If simulations can be performed to reveal the noise budget, the need for power and ground planes may be eliminated, and the designer will want to know this as early as possible in the design process. The tendency is to over-design the package, resulting in higher cost and complexity, because one can not be sure how the device will perform at the package level.

Another crucial issue to consider is time to market. When designers are operating without a clear idea of what's happening in the package or at the board level, there is a greater risk that the device will fail. It can quite easily violate the noise budget without the designers' knowledge, and the need for a different package design would not be discovered until the first bad run. This is certainly a cost issue, but it is really more of a time-to-market issue, because it can take 12 weeks to re-spin one of these packages.

Furthermore, PCB designers are now saying that they need to drive the package designs just as much as the IC designers do, because PCBs are becoming so complicated, expensive and difficult to route. Today's system design teams need the flexibility where customer requirements can drive the design either from the PCB level up into the chip, or from the chip down into the PCB. The package design is a critical intermediate part of the design either way.


Joel McGrath, technical marketing manager for advanced packaging technologies, can be contacted at Cadence Design Systems Inc., 270 Billerica Road, Chelmsford, MA 01824; 978-446-6104; Fax: 978-446-6798; E-mail: [email protected].

Physical IC Characteristics
Die size range: The acceptable IC sizes that fit into a given package.

Pad pitch: The distance between the center of adjacent bond pads on the die. (Note that this is different from pad spacing, the distance between adjacent bond pad edges.)

Escape routing: The routing required for conducting lines to reach the edge of the die from the interior.

Bond feasibility: A determination of whether or not all of the die pads can be wire-bonded using the prescribed rules.

Power/ground rings: Rings on a package surrounding the die that are used to bond power and ground nets and are part of the power distribution network.

Electrical IC Characteristics
Package parasitics: The impact of the package material and geometry on the integrity of the signals.

Solution analysis: A trade-off of factors initiated by the designer to achieve a certain performance level.

I/O buffers: Physical termination points on the chip for signals. I/O buffers can be different sizes depending on the signal strength required.

Constraint definition: Limitations the engineer can put on certain signals so that they are routed to a set of rules. An example of an electrical constraint would be the minimum or maximum length of a piece of conductor.

Power/delivery analysis: An evaluation of the power distribution around the circuitry to drive the device.

Physical Packaging Characteristics
Die size range: The acceptable IC sizes that fit into a given package.

Bonding patterns: A library of wire-bond patterns from which the user can choose.

Package libraries: A library of existing package designs.

The physical and electrical characteristics considered during IC and package design.
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Route feasibility: A determination of whether or not all of the die pads can be routed using certain rules.

Stack-up definition: The collection of layers (e.g., copper, dielectric, epoxy, soldermask) that make up an IC package.

Electrical Packaging Characteristics
Model libraries: A library of electrical models of existing packages used for board-level simulation.

I/O buffers: Physical termination points on the chip for signals. I/O buffers can be different sizes depending on the signal strength required.

Differential pair assignments: Assignments of pairs of nets that must be routed next to each other as closely as possible and equal in length within a certain tolerance. This is another example of an electrical constraint.

Physical boundaries: Package outlines.

Power distribution templates: Similar to libraries, these templates consist of known good power and ground networks that can be reused in different designs.


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