Meeting wrap-up

HD International conference reflects shifts in industry


SANTA CLARA, CALIF. – It was hard not to miss the optoelectronic bandwagon rolling through the HD International Conference in Santa Clara in April. Many companies were clearly shifting their focus to optoelectronic applications and finding significant new markets.

Karl Suss, Palomar Technologies and Semiconductor Equipment Corporation were on hand to discuss their laser diode attach machines. ESEC has also announced similar laser diode attach capabilities recently. These products are not revolutionary in their placement technology, because they simply leverage the precision placement capabilities of previous die attach equipment. What is unique is that they have been tailored for the specific challenges of laser diode attachment, including the high temperature of the eutectic gold process, scrubbing, very small die sizes and other factors associated with laser diodes. According to Klaus Ruhmer of Karl Suss, one of the biggest challenges is handling the optical fibers found in these products.

SST International had an interesting approach to precise placement of optoelectronics devices, using machined graphite inserts to force the chip into its position. The current accuracy does not match that of the equipment based on flip chip placement machines, but it is possible to envision etching processes creating similar templates for much more precise placement of devices.

Inspection equipment is another area where companies are extending their machines into the optoelectronic arena. Royce Instruments showed what they described as the only six-sided laser diode inspection tool. With cameras above, below and next to the laser diode, plus a mechanism that rotates the device 360 degrees about a vertical axis, all six sides of a laser diode can be viewed.

V.J. Technologies, a manufacturer of X-ray systems, had a product that uses an amorphous silicon detector instead of the more conventional CCD camera. The resulting increase in resolution can be used to identify the placement of an optical fiber inside a package, which is an important capability when the performance of an optical product is such a strong function of the alignment of the components.

Advances in Chip Thinning

If the industry's mantra is “smaller, faster, cheaper,” then researchers at University of Arkansas and Irvine Sensors Corp. are aiming to revise it to a more accurate, “smaller, thinner, faster, cheaper and more reliable.” Jedediah J. Young of the U. of Arkansas gave a presentation on the mechanical and morphological effects of thinning an integrated circuit (IC), as well as thermal management schemes used to operate a thinned IC at high power levels.

The need, or desire, for thin chips comes out of a host of advantages, including the fact that thin chips require less space, allow more functionality per unit volume (by stacking), increase power dissipation by improving thermal performance, and can conform to a curved surface. Because thin chips have more flexibility, they are also able to withstand higher coefficients of thermal expansion (CTE) mismatch. There are, however, potential disadvantages of chip thinning – namely, cracking of the chip during thinning, handling or attachment, and negative surface effects on the backside of the chip.

There are multiple ways to thin a silicon (Si) wafer, including plasma etching, backside grinding and polishing, laser chemical etching, wet chemical etching and focused ion beam processing. The researchers in Young's team, however, focused their study on plasma etching and backside grinding/polishing. Generally speaking, plasma etching has been found to cause no damage to the top surface of the wafer, nor to induce electrical damage to SiO2 layers or CMOS devices. Si wafers thinned by plasma etching do, however, exhibit a significant bow and some surface discoloration. Backside grinding/polishing, on the other hand, uses diamond wheel-based backgrinding equipment combined with stress management techniques to minimize damage to the wafer.

Thinned wafers were subsequently tested, and mechanical bending demonstrated a mechanical integrity of the chip after 10,000 cycles. Also, no degradation in electrical performance was detected after thermal cycling.

Atomic force microscopy (AFM) was used to analyze the surfaces of unprocessed, plasma-etched and polished surfaces. Thinning appears to reduce the large bumps that result from wafer dicing, although plasma etching causes pitting, and polishing causes grooves. The researchers concluded that the grinding-polishing method produces a more desirable surface.

Extensive thermal modeling of both wire bonded and flip chip ICs indicated that vias will slightly increase thermal efficiency, and that bottom cooling is a more efficient means of heat transfer than edge cooling. The University of Arkansas and Irvine Sensors will continue to study the residual stress induced on thinned chips, as well as developing additional thermal management schemes to increase the maximum operating power.

Built-in Rework Capability

While too much heat can be catastrophic to a package, it is conversely necessary in cases where packages must be heated for removal and rework before reattachment to a board. Mary C. Massey of TRW gave an update on an “Integral Heater for Reworking High Density Interfaces.” The presentation introduced the concept of an integral heater element that can be designed into any new custom microelectronics package (ceramic or plastic). This technology offers advantages that are not obtainable through the traditional method of heating an entire printed wiring board (PWB) assembly followed by localized hot gas removal of the part. This new method also is said to be ideal for providing localized heat for solder reflow attachment and removal processes for peripheral leaded and area array packages.

Successful rework using an integral heater
Click here to enlarge image

The researchers from TRW and Kyocera employed nichrome alloy in thin film sheets, and embedded heaters into high-temperature co-fired ceramic substrates. The heaters were placed adjacent to the package base to maximize heat transfer to the adhesive, while avoiding interference with the routing of circuitry layers above. The heater layer artwork can be easily modified to accommodate thermal or electrical ground vias to the package's bottom surface. The heater element is simply another layer of artwork, while the other attributes of the MCM package are unaffected from vendor package fab through PWB assembly.

TRW has implemented integral heater designs on current space flight hardware and is doing research regarding other applications. Massey succinctly said of the integral heater technology, “It's a built-in lifeboat. It's there if you need it.”

Lead-free Developments

Lead-free assembly continues to be a topic of great interest, and it had a prominent place at HD International as well. David Suraski of AIM presented an update on research on lead-free solder alloys as potential replacements for eutectic Sn/Pb, discussing their reasons for recommending a 96.2Sn/2.5Ag/0.8Cu/ 0.5Sb alloy with a melting range of 215-217 °C. He reported that the addition of antimony (Sb) improves properties and performance, as compared to Sn/Ag/Cu alloys. Sn/Sb was suggested as an option in response to an audience question about potential replacements for high-lead alloys.

Some of the difficulties of flip chip assembly on organic substrates were made clear during R. Wayne Johnson's (CAVE/Auburn University) presentation, which won the best paper of the session award. Both Sn/Pb and Sn/Ag/Cu showed opens and shorts after thermal shock testing, and cracks within the solders balls and the FR4 boards. The lead-free alloy performed worse than Sn/Pb. The results were highly dependent on the type of board used and suggested that a trench design was preferable.

Lead-free assembly can also be accomplished with conductive adhesives for applications requiring low-temperature processes, as shown in a talk on flip chip attachment of CdZnTe detector arrays by George Riley of FlipChips Dot Com. The arrays are bonded to alumina substrates with gold ball bumps and a silver-filled adhesive that cures at 65°C. The unfilled encapsulant used as an underfill cannot be co-cured with the conductive adhesive bumps, because the bumps will spread, potentially causing shorts.


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