3-D packaging infrastructure improving

Chandler, Ariz. – People have talked about 3-D packaging for years, and there have been many demonstrations of stacked chip configurations, including high-volume production of SRAM/Flash memory stacks for mobile phones starting around 1999. The packaging options and feasible applications are growing rapidly now, though, because of advances in key areas of infrastructure.

Jon Woodyard, product manager for 3-D packaging at Amkor, reports that such things as improved wafer thinning, cost-effective high-density substrates, increased availability of known good die, and better 3-D design tools have allowed the recent progress.

With wafer thinning, for example, the challenge is not removing the material from a silicon wafer, but handling the wafer without damaging it. The capability in the industry has reached the level of handling 50 to 150 µm thick, 8-inch diameter wafers safely if stress relief processes are used. Bumped wafers can also be thinned effectively now, with a thickness of 250 µm being attained. (See the report on the HD International conference in this issue for more discussion of wafer thinning processes.)

Known good die (KGD) availability does not necessarily mean that the ICs have been fully tested with one of the elaborate bare die test systems that are available. In some cases, it is just a matter of die yields being so high that they are effectively KGD. This is a good example of the necessity of carefully choosing the product that is being implemented in a 3-D packaging approach. As with any multichip configuration, a low-yielding die is not a good candidate for inclusion with other chips.

High-density interconnect substrates are critical for many 3-D applications in which some kind of redistribution is needed to accommodate the connections to two or more die. In some cases, there is even a redistribution layer on top of a chip. Apart from the industry-wide need for high-density interconnect, there is the added pressure in stacked configurations from chips whose bond pads are not optimized for a stacked assembly. For example, two ICs might have bond pads biased toward one side of the chip, and if those sides are lined up together, then there is an added requirement for high-density routing in the substrate in that area. According to Woodyard, cost-effective 2- and 4-layer substrates are allowing 3-D packaging to address more applications that have these kind of challenges.

Design and modeling tools for 3-D packaging are also improving, according to Woodyard. Previously, there was some amount of trial and error when seeing if a stack of chips and their wirebonds would create physical interferences, but geometric modeling tools now ensure that these problems are avoided in the design phase.

Many of the infrastructure improvements are indicative of an increase in the general level of understanding of the real issues that make 3-D packaging feasible. Much of this kind of education still needs to happen among the current and potential users of the technology, but there are signs of progress here. Sophisticated users of stacked packaging are currently designing ICs for stacking and putting redistribution layers on top of ICs at the bottom of a stack. Interestingly, Amkor's Woodyard has seen fabless IC designers being among the most advanced users of the technology, perhaps because they control the IC design and are accustomed to orchestrating the production at wafer foundries and packaging sub-contractors. An IC designer at an IC manufacturing company might have fewer options for incorporating the features needed for successful 3-D packaging.

3-D packaging is also seen as a quicker and easier way to integrate multiple ICs when compared to system-on-chip approaches. It is easier to change components in a stacked-chip package than it is to re-spin an SOC design. This flexibility allows the users to adapt to the demands of the marketplace in a timely fashion, which is especially critical when there is still much to be learned about all of the new chip integration technologies, whether on a wafer or in a package.

Electroglas introduces new probing and inspection systems

Munich, Germany – At SEMICON Europa, Electroglas Inc. introduced a new automatic wafer prober for parametric testing during front-end wafer processing. The new system, EG4/200e, is geared for the testing of wafer products for advanced RF communication devices. This kind of in-line parametric testing is becoming more important as the complex wafer processes require more tracking during the manufacturing flow, according to Electroglas VP Wayne Woodard.

The technology was developed by Electroglas with Cascade Microtech. An innovative wafer chuck, tuned cables, magnetic isolation, and a low-noise mechanical design are among the developments found in the new tool. These features result in lower system noise, leakage, and capacitance, which allow shorter measurement settling times.

Electroglas also introduced a new inspection system, QuickSilver IIe* for the automatic identification and classification of defects on processed semiconductor wafers at production speeds. The system detects and automatically classifies defects down to 1 micron, and it screens such flaws as passivation voids, scratches, and debris on the surface of wafers. The system also provides a detailed analysis of probe marks. The key technologies in the system include a proprietary CCD scanning camera and high-capacity buffer for capturing images of large die. One application would be the generation of defect maps before and after wafer bumping.

SECAP produces first 300 mm solder-bumped wafers

Kalispell, Mont. – Semitool Inc. and its partners in the Semiconductor Equipment Consortium for Advanced Packaging (SECAP) have successfully transitioned their solder-bumping process to 300 mm wafers. This is a significant step in establishing the feasibility of wafer-level packaging with the 300 mm wafer size that is proliferating throughout the semiconductor industry. SECAP was formed in September 2000 with the goal of developing equipment to facilitate the rapid acceptance of wafer-level packaging.

The product on the 300 mm bumped wafer had solder bumps down to 20 microns in diameter, with more that 4200 I/O on a 10 mm x 10 mm die. Semitool provided the plating technology, Karl Suss provided 300mm lithography equipment, Unaxis created the sputtered copper seed layer, Image Technology produced the mask, and the Fraunhofer Institute for Reliability and Microintegration coordinated the development. These five organizations are the charter members of SECAP.

Industry cycles aggravated by supply chain

San Jose, Calif. – Conventional wisdom says that the maturity of the electronics industry should dampen the cycles that have plagued it historically, but instead, the extra layers added to the supply chain in recent years have aggravated the cycles. This is according to “The Worldwide IC Packaging Market,” a new report issued by Electronic Trend Publications (ETP).

The fundamental problem is that with many vertical players – OEMs, contract assemblers, component distributors, and component manufacturers – the forecasts up and down the supply chain get distorted by estimates based on estimates based on estimates.

Click here to enlarge image

Because packaging is downstream in the semiconductor chain – at the tip of the whip – it can be affected very strongly by the cycles. ETP is predicting declines in both the revenue and the volume of packaged ICs for 2001, following a strong year in 2000. This will be the first decline in unit shipments since 1985.

Click here to enlarge image

Table 1 shows the projections out to 2005 for volume by package type. Predictably, the DIP package shows the lowest CAGR (-5.9 percent), and CSPs show the greatest growth (38.8 percent) during that time. The industry workhorse, the SO package, will grow at nearly the same rate as the industry as a whole, while retaining about 60 percent of the market. By revenue (Table 2), it is a different story, with BGAs providing the greatest revenue flow currently and through 2005.

Sources: Electronic Trend Publications
Click here to enlarge image

The price per I/O (Table 3) reflects the relative maturity of the products, according to ETP. DIPs, SOs, CCs, and QFPs all creep down around the half-cent per lead level with a -3 percent CAGR, while the prices for BGAs and CSPs shrink more quickly. The price per I/O for CSPs is predicted to be less than that for BGAs by 2002.

Another notable trend reported by Electronic Trend Publications is the growth of contract packaging as a fraction of the total market. In 2000, almost 20 billion units were packaged at a contract facility, representing 22.7 percent of the total. By 2005, it will be over 40 billion units, which will be 31.4 percent of the total units packaged. When measured by revenue, the contractors will be collecting over half of the dollars for packaging by 2003, in large part because they have focused on the high-end products such as BGAs.

Wafer-level packaging in production

San Jose, Calif. – Wafer-level packaging is looking more like a production technology all the time. Casio Micronics of Tokyo will be using Ultratech Stepper's Saturn Spectrum 3 steppers in its 6- and 8-inch wafer-level chip-scale packaging (WLCSP) production line, according to Ultratech. The WLCSP technology is being licensed from Integrated Electronics & Packaging Technologies, Inc. (IEP).

IEP is a joint venture formed in 1999 between Oki Electric Industries and Casio Computer Co. The technology was developed at Casio and spun out into IEP, an IP licensing and engineering support firm. IEP's WLCSP technology is already being used in at least two high-volume products, according to IEP's president and CEO Alex Tahara.

In an interview with Advanced Packaging magazine, Tahara said that Oki has been using IEP's WLCSP technology in a product for a watch, with a monthly volume of 50,000 units. It is a 4 mm x 6 mm device, with 79 pins at 0.5 mm pitch. This has been in production for more than a year. The other announced product, which also went into production in 2000, is the PCM sound LSI or “melody chip” in certain cell phones in Japan. This chip is in a 6.3 mm square WLCSP, with 47 pins at 0.8 mm pitch. Its volume is about 100,000 per month. Tahara said that the next product announcements for IEP's technology are expected to be in cell phones, printers, and global positioning systems (GPS).

Figure 1. IEP’s wafer-level CSP technology.
Click here to enlarge image

IEP's technology (Figure 1 on page 22) consists of sputtered TiW/Cu layers for the under bump metallurgy (UBM), Cu re-distribution layers, and electroplated Cu posts embedded in an epoxy layer. The epoxy is transfer molded at the wafer level, and the proprietary material and process were co-developed with the material supplier. It meets heightened stability and reliability requirements, and it also serves as a mechanical support for the package. The silicon wafer can be thinned to the 50 to 200 micron range, with the 100 micron thick epoxy making the wafer robust enough for the thinning process.

Altra Broadband opens Boston technology center

PITTSBURGH – Altra Broadband Inc., a subsidiary of Ansoft Corp., has opened an R&D facility in Burlington, Mass. The Boston Technology Center will focus on mathematical modeling and algorithm development for broadband fiber optic and wireless communications. The team in Boston includes Jacob White, professor of electrical engineering at MIT, Mary Tolikas, an expert in systems dynamics, Deepak Ramaswamy, an expert in mathematical modeling of coupled-domain systems, and David Abrahams, a Carnegie Mellon graduate who recently developed speech recognition and transcription solutions for wireless devices.

Packaging affects copper/low-k wafer processing

SAN FRANCISCO – The roadmaps guiding the progress in silicon wafer processing require copper as the interconnect material, and new low dielectric constant (k) materials as the insulator in which the copper interconnect is embedded. In what might be a surprise to veterans of the packaging industry, the packaging processes are actually playing a significant role in the development of these emerging wafer processes.

Many of the new low-k materials require porosity to achieve the low dielectric constant required for upcoming generations of CMOS devices, with the air pockets lowering the effective dielectric constant of the material forming the insulating layer.

However, the porosity significantly affects the robustness of the structure, which has created problems during wire bonding and other packaging processes in which stress is applied.

IBM handles this by embedding dummy metal vias in the dielectric layers below wire bond pads, according to Jeff Hedrick, who presented the latest IBM low-k work at the Spring Meeting of the Materials Research Society (MRS). Hedrick also said that IBM uses a stronger – but higher-k – material for the upper two layers of insulator in the eight metal layer interconnect structure. The electrical performance is therefore compromised slightly to increase the compatibility with packaging processes.

An alternative low-k material from Applied Materials is stronger and can therefore be used in all of the insulating layers in the interconnect of an IC. Hichem M'Saad, who gave Applied's update at the MRS Spring Meeting, emphasized that its material is the only low-k material that has been integrated in all eight copper layers of the latest chip technology because it is fully compatible with standard packaging processes. It is an encouraging sign for the industry that packaging is being taken into account as the latest silicon processing technologies are developed.

“Green” molding compounds developed

SAN FRANCISCO – Plastic molding compounds typically contain brominated materials and antimony trioxide to act as flame retardants, a requirement that grew out of frequent fires arising in the electronics inside television sets many years ago. More recently, it has been discovered that bromine-based flame retardants may produce carcinogenic dioxins, and that antimony trioxide is also a carcinogen. Research by Dexter Electronic Materials is identifying safer flame retardant alternatives for molding compounds.

In a paper presented by Anthony Gallo of Dexter at the Spring Meeting of the Materials Research Society, transition metal oxides were evaluated as a replacement for the less environmentally friendly materials currently being used as flame retardants. Molding compounds with these transition metal oxides pass international standards for flammability, and they pose less of a hazard to the environment. They also have excellent high-temperature reliability, which was a problem for phosphate esters, another set of materials that has been proposed as an alternative to the transition metal oxides.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.