Emerging technologies in bumped interconnections
BY GLENN RINNE
Solder bumping for flip chip packaging was developed in response to the continuing demand from the electronics industry for devices that are smaller, faster and more economical to produce. A general overview of emerging technologies for chip connections requires a discussion of the history of bumps and bump-like structures. From the hundreds of examples of attempts to create an elongated solder bump for flip chip style packaging, a few of the more interesting and revealing methods are discussed here.
Changes in the temperature of a flip chip assembly cause expansion or contraction of both the chip and the substrate, although at different rates. The difference in expansion or contraction results in the displacement of the pads on the chip relative to the pads on the substrate, particularly at the corners of the chip. Because solder connects these pads and because solder is much more elastic than either silicon or the substrate, the solder must stretch or contract to accommodate the displacement.
Figure 1. Rockwell's layered solder column.
All materials have an elastic limit. Stretched beyond this limit, all materials undergo plastic deformation that is permanent. The damage of repeated plastic deformation accumulates until the solder joint fails. The simplest solution to this problem is to design the system such that the elastic limit is never exceeded. This means that the maximum displacement divided by the length of the solder bump should not exceed the limit for the solder alloy, typically one or two percent. This is the motivation for making solder bumps in the form of long cylinders or posts. Because solder has a low melting point, special attachment methods must be devised to ensure that the final bump shape retains the desired profile.
A Brief History
Optoelectronic technology requirements motivated engineers at Rockwell International to develop a solder column technology more than 20 years ago. Columns were formed on the chip through repeated steps of coating and patterning photoresist and plating solder.1 Multiple layers of plated solder were built up to form tall, narrow columns (Figure 1). After the final plating step, the tops of the posts were polished flat to improve planarity and a cap metal was used to prevent oxidation. The chip was then bonded to the substrate by reflow, thermocompression or diffusion bonding. Finally, the photoresist was removed with solvent.
Figure 2. AMP's wire-reinforced solder column.
Nearly 15 years ago, AMP proposed that flux-cored solder wire could be manufactured with copper wires laid in the core along with the flux. The solder wire was then cut to short lengths and loaded into holes punched in a sheet of water-soluble paper. The paper was aligned to the pads on a chip or board and reflowed (Figure 2). The copper wires prevented the collapse of the solder and preserved the columnar shape.2 A final aqueous cleaning step dissolved the paper carrier.
Contemporary with the AMP solution, Nippon Telephone and Telegraph (NTT) proposed a novel bump stacking approach.3 Here, a thin (about 25 µm) polyimide film was fabricated with an array of vias matching the array of pads on the chip. Solder bumps were then formed on the vias on both sides of the film. The bumped film was aligned between the chip and the board and reflowed (Figure 3). This approach increased the bump height by a factor of two or three without sacrificing bump pitch.
Figure 3. NTT's stacked-sphere technology.
In the 1990s, LSI Logic disclosed a metal casting method of forming non-equilibrium shaped solder bumps.4 Using this method, a mold was fabricated containing cavities or wells in the desired shape of the final solder connection. A manifold connected each well to the liquid solder pump. When a chip or substrate was placed in the mold and solder was injected through the manifold to the cavities, the molten solder would wet the pads on the chip, thus bonding the solder bumps to the pads. Upon cooling and solidifying the solder, the chip was removed with the solder bumps attached.
Figure 4. Motorola's extended eutectic solder post.
At about the same time, Motorola patented a method of making solder columns using the well-known C-4 evaporation process. Evaporation of solder alloys had the characteristic of fractional distillation of the components due to the different enthalpy of vaporization of the alloy components. In other words, for lead-tin solder evaporation, the lead was evaporated first, then the tin. In the classic C-4 process, the reflow process homogenized the bump, and this brought the tin down to the under bump metallurgy (UBM) interface where the bonding reaction took place. In the Motorola method, a layer of tin was evaporated first, using a separate tin source, and then the thick layers of lead and tin were evaporated.5 During the joining reflow step, the thin tin layer bonded the bump to the chip and the top tin layer bonded the bump to the substrate (Figure 4). Because the melting point of lead was never reached, the column of lead did not collapse.
Intel followed quickly with a patented method that was similar to the current ball-loading technique. In the Intel method, a roll of flexible tape carried solder preforms and maintained both the position and orientation of the solder balls during the alignment and bonding process.6 The tape was either removed after bonding the solder columns to the chip or left in place to support them.
Figure 5. Fujitsu's wire interconnect technology.
A technique developed by Fujitsu called wire interconnect technology (WIT) was originally patented in 1992, and most recently patented in 1998. In the WIT method, copper pillars are soldered to both the chip and the substrate (Figure 5).7 The innovation in this approach is that electroplated rings of solder on the chip provide the solder needed to join the pillars to the chip. The copper pillar is then electroplated with its base inside the solder ring. At the reflow step, the plated solder ring secures the pillar to the chip with a meniscus. The meniscus provides the important function of distributing the stress that would otherwise concentrate at the corner of the post-to-chip interface.
All materials expand or contract with changes in temperature at different rates depending on their coefficients of thermal expansion (CTE). When two different materials (for example, solder and substrate) are bonded tightly together and subjected to temperature changes, tensile stress will develop in one material and compressive stress in the other, causing strain in both materials.
Figure 6. Tessera's etched copper post structure.
If the strain never exceeds the elastic limit, there is no cyclic fatigue damage in the solder and the thermal cycle failure rate becomes immeasurably low. The desire to reduce maximum strain to below the elastic limit has created an interesting variety of solutions that range from spheres to springs.
Figure 7. FormFactor's wire skeleton solder column.
Just this year, there have been several patents relating to bumping methods for non-equilibrium shapes. One method from Tessera, typically used with microelectronic devices, forms copper columns on polyimide tape by subtractively etching copper foil.8 This interconnection method consists of a flexible support structure attached to a conductive sheet. When the conductive sheet is selectively removed, the resulting coplanar columns form an interconnection between the device and the substrate. Due to the nearly isotropic removal of material during etching, the columns assume a conic profile, thus reducing the stress concentration that might be present if the column-to-polyimide intersection were 90 degrees (Figure 6). The tape is then applied to the face of the chip by adhesive and electrical connections are made by wirebonding or modified tape automated bonding (TAB).
Another recent approach was developed by FormFactor. To build a non-equilibrium solder post, this method uses a skeleton of nickel-coated gold wire to support the solder.9 The assembly involves two substrates, each with a set of contact pads. The contacts are connected by freestanding, springable interconnects. Using a modified wirebonder, gold wire is ball bonded to the metal pad on the chip. The wire is drawn through a tight, tall loop. The second bond is stitched next to the ball bond on the same pad. This forms a loop above the surface of the chip. A second loop is formed on the same pad, adjacent to the first loop. After all the loops have been formed, they are passed through a solder wave. Solder wets and bridges the adjacent loops, forming solder posts (Figure 7).
Figure 8. FormFactor's spring technology.
A variation on the FormFactor scheme creates solder-coated springs to provide raised contacts on the surface of electrical components.10 In this modification, gold wire is ball bonded to the pad on the chip, formed into an “S” shape by translation of the capillary, with a ball at the end formed by electrical discharge. The wire is then plated with tin or solder such that the tin hardens the gold wire by forming the eutectic alloy (Figure 8). This process results in added resilience of the wire stem and increased security at the wire stem termination.
Conclusions and the Future
These creative solutions, and many others, have been developed with the intent of reducing the maximum strain to below the elastic limit. While each achieved the goal to some extent, none has been widely adopted, primarily due to cost factors, including materials, processing, testing, assembly and rework. However, the more stringent requirements of emerging high-power, RF and optoelectronic applications are changing the rules to an extent that perhaps some of the past solutions will find utility. More probably, the variety of solutions previously proposed will catalyze the innovation of more elegant and viable solutions. AP
- J. M. Tracy, “Method of Fabricating an Array of Flexible Metallic Interconnects for Coupling Microelectronics Components,” US Patent #4,067,104, 1978.
- D. G. Grabbe, “Compliant Interconnection and Method Therefor,” US Patent #4,642,889, 1987.
- N. Matsui et.al., “VLSI Chip Interconnection Technology Using Stacked Solder Bumps,” IEEE Transactions on CHMT, 12 (4), pp. 566-570, Dec. 1987.
- R. T. Trabucco, “Casting of Raised Bump Contacts on a Substrate,” US Patent #5,381,848, 1995.
- S. E. Greer, “Semiconductor Device Solder Bump Having Intrinsic Potential for Forming and Extended Eutectic Region and Method for Making and Using the Same,” US Patent #5,470,787, 1995.
- J. F. McMahon and G. Chiu, “Tape with Solder Forms and Methods for Transferring Solder to Chip Assemblies,” US Patent #5,497,938, 1996.
- D. G. Love et.al., “Wire Interconnect Structures for Connecting an Integrated Circuit to a Substrate,” US Patent #5,773,889, 1998.
- J. C. Fjelstad, “Connection Components with Posts,” US Patent #6,177,636.
- I. Y. Khandros, “Method for Manufacturing Raised Electrical Contact Pattern of Controlled Geometry,” US Patent #6,215,670, 2001.
- I. Y. Khandros, “Method of Mounting Freestanding Resilient Electrical Contact Structures to Electronic Components,” US Patent #6,049,976, 2000.
Glenn Rinne, vice president of research and development, can be contacted at Unitive Advanced Semiconductor Packaging, P. O. Box 14584, Research Triangle Park, NC 27709-4584; 919-941-0606; Fax: 919-941-5097; E-mail: [email protected].