“Twenty-five years ago, there was no e-mail, no faxes, no Internet and no PCs,” said Myers. “And though technology has admittedly made all of our jobs easier, success still boils down to the basics of business: service, quality, a fair price and products that are delivered on time. Companies that remain focused on that will remain in business; that’s what we try to do here.”

International Workshop on Wafer Level CSP and Flip Chip Packaging
The IEEE Components, Packaging and Manufacturing Technology Society, in cooperation with ASME Electrical and Electronics Packaging Division, the American Ceramic Society, IZM Germany, and the Packaging Research Center, invites abstracts for the International Workshop on Wafer Level CSP and Flip Chip Packaging, to be held March 1-3, 2002, at the Evergreen Marriott Conference Resort in Stone Mountain, Georgia.
Abstracts should focus on one of the following topics: wafer level packaging processes, wafer packaging materials, wafer level burn-in and test, wafer package reliability, small die and memory products, ultra high-density substrate technologies for WLP, new and advanced wafer technologies, wafer level research around the world, and nano wafer level packaging.
Abstracts should be sent electronically to [email protected] by November 19, 2001. Questions should be directed to general chair Rao Tummala at the Georgia Institute of Technology, [email protected].