Zuken addresses time-to-market with predictive analysis tool

WESTFORD, MASS. – Zuken USA, in a response to the need for more proactive IC packaging tools, has released the Package Predictor. This analysis tool aims to bridge the gap between IC design and package manufacturing to decrease time-to-market by up to 30 percent.

Quick time-to-market can be a difficult goal, with typically two to four weeks of “dead time” between design and package house; during this interim stage, discovering major errors, such as the package house having the wrong netlist, can lead to lengthy design iterations. It is this type of time-consuming problem that the Package Predictor is designed to eliminate.

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The tool aims to optimize IC die pad positioning, connection list and substrate layout for better design and manufacturing reliability. It allows IC designers to visualize first-hand physical placement of nets and critical nets, substrate bond fingers, and power rings, and make any necessary changes before it is passed to the packaging house.

Les Ammann, director of advanced packaging technology at Zuken, said, “Lengthy data exchange, data manipulation steps and unrealistic connection lists cause delays. This tool is a link between the packaging house and its customers, enabling IC designers to deliver a realistic manufacturable proof of package design. Delivering shorter design to market time at this late stage is critical.”

The Package Predictor also aids in making critical decisions, such as two-layer vs. four-layer, or wirebond vs. flip chip. It is designed for use with CSP, stacked die, MCM, flip chip and PBGA technologies.

The tool also is said to examine packaging in three dimensions, allowing 3-D design rule checking around wirebonds and instantaneous 3-D viewing of wirebond shells. This capability allows a more realistic bond shell to be created accurately by proofing overlapping wirebond clearances before the design reaches the manufacturing floor.

Ammann indicated that Zuken plans to begin promoting to the market and release a Version 1.0 by late summer.

Adept university program

SAN JOSE, CALIF. – Adept Technology Inc., a manufacturer of flexible automation for the telecommunications, fiber optic and semiconductor industries, recently announced a university program to provide robotic hardware, controllers and software to colleges and universities. The systems consist of an Adept C40 controller with AIM application software, AdeptWindows software and a 3-axis AdeptModules mechanism. Four system configurations are available at discounts up to 80 percent, and include Adept's support and customer service.

“We feel it is extremely worthwhile to subsidize advanced research and curriculum within the university community,” said Joe Campbell, vice president of marketing for Adept. “Students will gain valuable hands-on experience with industry leading technology, which benefits the entire automation industry.”

Global market to rebound in 2002

REDWOOD CITY, CALIF. – The Semiconductor Industry Association (SIA) has released a midyear forecast projecting an industry-wide recovery in the second half of this year that will spur growth of 20.5 percent in 2002 and 25 percent in 2003.

“Despite the sales decline brought on by the excess inventory this year, the semiconductor market is still projected to grow from $140 billion in 1999 to $283 billion by 2004, a compound annual growth rate of almost 14 percent,” said Kirk Pond, Fairchild Semiconductor's president, CEO and chairman of the board. “The industry has a 17-percent compound annual growth rate for the past 40 years and we expect that to continue for the foreseeable future despite periodic cycles.”

In the mid 1980s, the semiconductor industry experienced a similar cycle of extremely strong growth with an inventory correction in the following year. However, the 16.5 percent downward adjustment in 1985 was more severe than the 14 percent currently being experienced.

Pond went on to note that the industry can now react faster to changing market conditions because of instantaneous communications and better market intelligence.

“If you look at the downturn starting in 1996, the industry took 12 quarters before reducing capacity. In 2001, the industry took action with the first signs of the downturn and began reducing its capacity in only two quarters,” said Pond.

The Americas market is forecasted to remain the world's largest in sales revenue during the next four years, with the Asia Pacific market closing in. The Japanese and European markets will be close behind.

The SIA forecast for 2002 includes total semiconductors growing by 21 percent, discrete components by 19 percent, optoelectronics by 16 percent, analog by 25 percent, MOS logic by 17 percent, MOS micro devices by 16 percent, microprocessors by 11 percent, microcontrollers by 21 percent, digital signal processors by 30 percent, MOS memory by 29 percent, DRAM by 29 percent, and flash by 35 percent.

Murata expands component lines with advancements in passives

SMYRNA, GA. – Murata Electronics North America has expanded its line of components for high-speed, telecommunications, computer and automotive applications. Murata's chip inductors (LQ series), capacitors (GRM/GA series) and EMI filters (BLM/NF series) combine passive components with integrated circuits for use in telecommunications broadband digital subscriber line (DSL) modems, and other wired and wireless devices.

These expanded component series also allow designs for advanced technologies, such as voice over DSL, because of their compact size, speed and placement flexibility.

“To meet the needs of these rapidly expanding markets, we've worked closely with equipment manufacturers to provide them with the best products designed to meet the growing demands of their end-users,” said Gerry Hubers, market segment manager for Murata.

Murata's hi-cap multilayer chip capacitors boast 1,000 layers with dielectric thickness of less than one µm. Other recent developments include a movement toward lead-free components with the use of tin-silver plating, and collaborative work with IBM on a D-cap design.

New study investigates flip chip market

AUSTIN, TEXAS – A new study entitled “Flip Chip Markets and Infrastructure Developments” has been released by TechSearch International. Flip chip has expanded in two major areas – one driven by the high-performance needs of the microprocessor, ASIC and high-end DSP devices, and the other driven by form factor where die sizes are small and packaging cost must be as minimal as the package itself.

What's new in flip chip technology is its expansion into the interconnect realm previously dominated by wirebond. It is the potential expansion of flip chip into the mid-range pin counts that represents a shift in the adoption of the technology, improvements in the industry infrastructure, and a maturing of the industry – reflected in cost reductions.

Another new development is the introduction of wafer-level packages (WLPs). Many low pin count devices are marketed as WLPs, and many WLPs are fabricated using virtually the same bumping process as used for conventional flip chip bumped die. While this low pin count application represents millions of die, few wafers are required because thousands of parts can be produced on a single wafer.

The market report examines growth in terms of die and wafers, bumping capacity, supply and demand projections, and flip chip markets by application. For more information on the report, visit

Atlantic Technology, qualified and recognized

Crumlin, South Wales – Atlantic Technology, Europe's largest IC probe, assembly and RF test services subcontractor, has received QS9000 third edition certification by Lloyds Register Quality Assurance. The next challenge for the facility will be securing ISO14001, the environmental standard that the company is currently working toward.

In related news, Atlantic was recognized by Teradyne as an industry leader in subcontract mixed-signal and RF test. The award was presented to Atlantic's worldwide test director, Mohamed Djadoudi, at a ceremony at SEMICON Europa in April.


The equation on page 36 of the May 2001 issue (“Plasma Technology and Integrated Circuits”) should have read: 1=(kT/s2P). We regret the error.


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