TAEC introduces EDRAM core with 12-ns access time for SRAM replacement

August 29, 2001 – Toshiba America Electronic Components, Inc. (TAEC) today announced that its fast access embedded dynamic random access memory (FADRAM) core with an access time of 12-nanoseconds (ns) and a typical latency of 1 clock cycle has been silicon validated for use with the company’s TC260 technology library for application specific integrated circuits (ASICs). The access time was measured using a 4Mb core; smaller cores can produce faster access times.

TAEC also announced availability of five new high-speed SerDes (Serializer/Deserializer) input/output (I/O) macros, production-proven MIPS RISC 64-bit and 32-bit processor cores and the ARM9 46E-S processor core.

The company said its FADRAM core is ideal for power-sensitive, high-speed networking and data-communications applications that otherwise would rely upon embedded static random access memory (SRAM), which can consume four times the silicon territory and much greater power.

“ASIC designers who design chips for such applications as high-speed packet-processing can now increase on-chip fast-access memory yet still stay below their power budgets by using Toshiba’s FADRAM instead of SRAM cores,” said Peter Richmond, business development director, system IC business unit. “Our 3.125 gigabits/second (Gb/s) SerDes I/O macros also reduce power and pin count in chip-to-chip and backplane interfaces.” There are three SerDes macros for asynchronous I/O and two for synchronous I/O, including one for direct optical interface that supports SONET applications.

The TC260 product family is based upon Toshiba’s 0.18-micron (0.14-micron drawn gate) CMOS process, which enables the fabrication of very dense, high-performance embedded DRAM without compromising the performance of on-chip logic. TAEC also offers a TC280 0.13-micron (0.11-micron drawn gate) technology.


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