IMAPS flip chip event targets an eager audience
BY KATHLEEN M. PETERSON
The IMAPS Workshop and Exhibition on Flip Chip Technology drew technologists to Austin, Texas, in mid June for three days of professional development courses, paper presentations and a tabletop exhibition. Co-sponsored by the Central Texas Electronic Association, the workshop was an outgrowth of the IMAPS Flip Chip Advanced Technology Workshop, which has been held for the past three years in Georgia.
Flip Chip 101
“Flip Chip Technology: Bumping, PWBs, Assembly and Reliability” was taught by R. Wayne Johnson of Auburn University. Johnson opened by saying, “It would be nice if I could come in here and say, 'Okay, guys – here's how you do it.' Then we could all go home with a cookbook and do it. But there's always a trade-off.”
In that vein, Johnson detailed the pros and cons of different flip chip assembly methods with four areas of focus: bumping, substrates, assembly and reliability. The perceived limitations to the use of flip chip, including the need for underfill, limited pre-test and known good die, the challenges of rework, and die availability, might account for the fact that 95 percent of die are still wirebonded.
Interconnection options for flip chip include solder, conductive adhesive and thermo-compression. Johnson indicated that Flip Chip Technologies has tested an 85.9Sn/10In/3.1Ag/1Cu alloy that performs well but which has not yet found widespread use. Likewise, Polymer Flip Chip Corp. has introduced a successful conductive adhesive. For specialty applications, such as microwave, RF, high-temperature or optical applications, the use of thermo-compression with gold bumps can also be ideal.
When designing flip chips, substrate choice can be crucial. Dielectric layers can be reinforced or non-reinforced, and vias may be photoimaged, laser drilled or plasma etched. While the “dog bone” design for wiring and vias is traditional, the space for vias decreases as pitch gets finer, which makes via-in-pad technology more attractive. Another issue regarding substrates is the surface finish. A common approach is to use electroless nickel/immersion gold, although there has been recent interest in other materials, such as organic surface protectant, palladium, silver and tin.
Johnson indicated that flip chips are relatively easy to rework before underfill, but that they require more sophisticated methods after underfill. Currently, however, some thermally reworkable underfills are in development. Johnson called wafer-applied underfills “the ultimate holy grail.” Such underfills employ the same concept as no-flow underfill except they are applied at wafer level, forming a solid film. This technology, which is only in the development stage, will eliminate dispensing, may eliminate post reflow cure, and may be reworkable.
KGD Technologies for Flip Chip
Concurrently, Larry Gilg of the Die Products Consortium taught a professional development course entitled “Known Good Die Technologies for Flip Chip.”
Gilg pointed out many of the challenges associated with system-on-chip and system-in-package, including the fact that dissimilar semiconductor technologies can increase cost beyond the value of the integration benefit. He attributed the interest in flip chip to performance, form factor and cost. Unfortunately, there are still barriers and challenges when it comes to flip chip technology, and the lack of standards for KGD is high on that list.
Reliable test methods for KGD are still on the horizon. There is a need for wafer-level test, which will require new equipment and a shift in paradigm. It is important to note that a combination of high incoming die quality and high test coverage is needed to achieve acceptable rework and defect levels. One of the major challenges to be addressed is how to handle and pack die most effectively and safely; options include carrier tape, surf tape, Gel Paks, chip trays and film frames. The industry has yet to standardize on this issue.
The paper sessions at the workshop focused on a myriad of challenges, including assembly and reliability issues, underfill technology, bumping and interconnect, lead-free flip chips, and modeling. Douglas Katze of Emerson & Cuming (Billerica, Mass.) presented a new generation of no-flow fluxing underfill that is easy to process, uses a standard reflow profile and requires no post cure. Donald J. Hayes of MicroFab Technologies Inc. (Plano, Texas) provided an update on a solder application method that uses ink-jet printing technology. Hayes reported that the technology can place 25 to 125 µm diameter bumps onto wafers, PCBs, MEMS devices, VCSEL arrays and other substrates to tolerances of better than ± 5 µm.
Another type of underfill technology that was presented at the conference is advanced non-conductive paste, which creates solder joints by curing rapidly after solder reflow. Osamu Suzuki of NAMICS Corp. (Niigata-City, Japan) presented data regarding its reliability.
In a presentation entitled “Flip Chip Applications in Sensors,” Glenn Rinne of Unitive Electronics Inc. (Research Triangle Park, N.C.) noted that “Sensors are more secret than photonics.” Reminding us that sensors require access to and protection from the environment, Rinne pointed out the specific challenges of packaging for devices such as a tiny camera that a patient swallows in order to photograph the digestive tract for diagnostic purposes. A variety of sensors, including automotive optical sensors, chemical sensors, tactile sensors and thermal sensors, often require new innovations because traditional packaging methods don't always apply.
Next year's flip chip event will be held June 16-19, 2002 at the Four Seasons Resort in Austin, Texas.