September 21, 2001 – Geneva, Switzerland – STMicroelectronics has introduced its latest generation of chip-scale package for power integrated circuits as well as six N-channel MOSFETs that take advantage of the new package to slash size and weight while boosting thermal and electrical performance.
The PowerFLAT case, available in 6 x 5mm and 5 x 5mm outlines, adopts a micro-lead-frame design that, partly by replacing leads with terminal pads, ushers in nothing less than an entirely new chip-packaging concept. Power devices ensconced in the PowerFLAT package will find wide acceptance in DC-DC converters and the battery management sections of portable equipment, according to the company.
Of the two outlines unveiled, the 6 x 5mm PowerFLAT case is pin compatible with a standard SO-8 package, yet accommodates 118% more die area. Moreover, both outlines feature an exposed back slug that connects the MOSFET die to the printed circuit board for superior heat dissipation, ST said. The maximum height of the PowerFLAT is just 1mm. In addition to its light weight and small size, the company claims the PowerFLAT package reduces parasitic inductance to yield better MOSFET performance.
Riding the roll out of the PowerFLAT packages are six N-channel MOSFETs boasting high efficiency and solid performance. Offered in the 5 x 5mm outline version are the STL22NF10, with a 100V drain-source breakdown voltage (BVDSS), 65m(ohm) typical on resistance (RDS(on)), and 22A continuous drain current (ID); the STL28NF3LL, with a V(BR)DSS of 30V, a typical RDS(on) of 5.5 m(ohm), and an ID of 28A; and the STL4NM60, with a 600V BVDSS, 1.5(ohm) RDS(on) (typical), and 4A ID.
The remaining family members harnessing the 6 x 5mm case comprise the STL30NF3LL, with a BVDSS of 30V, a typical RDS(on) of 6m(ohm), and an ID of 30A; the STL35NF10, with a 100V BVDSS, 25m(ohm) typical RDS(on), and 35A ID; and the STL35NF3LL, with a 30V BVDSS, 6m(ohm) typical RDS(on), and 35A ID.
All six new PowerFLAT MOSFETs use ST’s second-generation STripFET technology, which yields transistors having a very low on-resistance and minimal gate charge, the company said. As a result, devices show a dynamic performance that is superior to the closest competition. In addition, the STL4NM60 plies a MOSFET technology that combines a multiple-drain process with ST’s horizontal layout. The benefit to the design is a very low on resistance, very high dV/dt and impressive avalanche characteristics.
Samples are available now for the STL22NF10 and STL30NF3LL and are forthcoming in September for the remaining PowerFLAT family MOSFETs.