ASE launches volume production of wafer-level chip scale packages

October 11, 2001 – Santa Clara, CA – Advanced Semiconductor Engineering Inc., a semiconductor packaging and testing company, will launch volume production of wafer-level chip scale packages (CSP) this quarter, ramping up to 2.4 million chips/month.

ASE’s wafer-level packaging capability is based on Kulicke & Soffa’s Ultra CSP, licensed in January 2001. A CSP has a packaged size of no larger than 120% of the naked die.

Wafer-level chip scale packaging is gaining prominence to accommodate the increasing demands of wireless communications and portable consumer electronics. Semiconductor chips in such applications require high levels of electrical performance, miniaturization, and reliability. Wafer-level chip scale packaging has found great success in memory and integrated passive components.

A recent survey by Prismark, an electronics industry consulting firm, indicated that worldwide consumption for wafer-level CSPs amounted to 85 million units in 2000. Of this amount, integrated passives accounted for 20 million units. Prismark projected that the worldwide consumption of wafer-level CSPs will reach 3.44 billion units with integrated passives reaching 2.4 billion units in year 2005. Wafer-level CSP has now also found wide acceptance in analog devices, voltage/power regulators, and power amplifier applications.

“The move towards wafer level CSP is an inevitable step as it supports our customers’ desire to quickly develop chips that are smaller, faster, more powerful and lower in manufacturing cost,” said J.J. Lee, VP of research & development, ASE Group. “In developing our wafer level packaging techniques, ASE places great emphasis in training our engineers to handle wafers and equipment,” he added.


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