Get2Chip, Verplex to provide implementation, verification flow for SOC designs

October 22, 2001 – San Jose and Milpitas, CA – Get2Chip and Verplex Systems have partnered to provide a system-on-chip (SOC) design flow based on Get2Chip’s VOLARE multi-level synthesis platform and Verplex’s conformal logic equivalence checker (LEC).

Get2Chip and Verplex intend to provide a seamless flow between synthesis and formal verification as a means of reducing design implementation and verification time. The companies say the result of this cooperation will be a high-capacity and high-performance solution targeted toward the design and implementation of complex, multi-million gate SOCs.

“By teaming VOLARE and conformal LEC together in a common environment, we can guarantee fast and accurate functional convergence between the register-transfer level and the gate-level netlist,” notes Lauro Rizzatti, Get2Chip’s marketing director. “The integration of VOLARE with Conformal provides designers with a consistent design flow that is powerful, accurate and easy to use, enabling better productivity.”

“The proliferation of ultra-deep submicron processes with geometries below 0.25-micron is forcing designers to adopt new design methodologies and tools to handle the increased complexity,” adds Ralph Sanchez, product marketing manager at Verplex. “With the two companies working this closely together, we expect to improve both the quality of results and the schedule of advanced SOC design development.”


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