October 15, 2001 – San Jose, CA – LSI Logic Corp. announced the second generation of its ZSP digital signal processor (DSP) architecture at the 2001 Microprocessor Forum in San Jose, CA.
Building on the ZSP400 superscalar DSP, the new second generation (G2) architecture offers increased processing performance, reduced power consumption, and an enhanced feature set and instruction set architecture (ISA), the company said, while maintaining backward compatibility.
Architectural innovations include a hardware-scheduled pipeline, high-bandwidth memory architecture, a flexible co-processor interface, enhancements for conditional and bit-level operations, and extended debugging capabilities including trace and profiling features. Exploiting the inherent scalability of the architecture, LSI Logic plans a family of cores spanning a range of requirements from high performance to extremely low power consumption.
“We’ve had success with the original ZSP superscalar architecture licensed by Broadcom, IBM, Conexant and others,” said Giuseppe Staffaroni, VP and GM of LSI Logic’s Broadband group. “The ZSP G2 architecture extends our offering to the highest levels of signal processing performance. Our licensees can leverage the capabilities of this architecture to realize optimal system-on-chip solutions for the next generation of communications products.”