October 2, 2001 – Wilsonville, OR – Mentor Graphics Corp. announced new patent pending Design-for-Test technology called Embedded Deterministic Test (EDT) that extends the capacity of automatic test equipment for a reduction in the cost of semiconductor testing, which can represent as much as 50% of manufacturing costs.
Mentor’s first EDT product, TestKompress, employs the new compression technology that allows semiconductor manufacturers to reduce the ATE memory and time requirements for testing ASIC, IC and SoC designs by up to 10 times, according to the company.
According to Prime Research Group, the semiconductor industry spent $4.9 billion in 2000 on digital IC and SoC tester purchases. At least 60% ($2.9 billion) of this investment was made to meet the increased capacity requirements. The shift from 200mm to 300mm wafers by many manufacturers and the use of new fault models to detect failure mechanisms associated with deep sub-micron designs are expected to continue to drive the need for additional test capacity.
“While the cost of semiconductor manufacturing continues to drop sharply year after year, the cost of test has continued to rise due to skyrocketing gate count, increasing complexity, larger wafer size and changing process technology,” said Walden Rhines, chairman and CEO of Mentor Graphics. “From a purely economic standpoint, the impact that EDT technology will have on the semiconductor manufacturers in terms of reduction in capital spending could make TestKompress one of the most important product introductions by Mentor.”
TestKompress is compatible with scan and automatic test pattern generation design-for-test flows, according to Mentor Graphics. TestKompress uses the same scan DFT methods, script files and ATPG libraries as Mentor’s FastScan product. The solution also supports all scan methodologies and fault models, Mentor Graphics said. Additionally, TestKompress uses the same test vector formats and tester interfaces enabling seamless and intuitive ATE integration and adoption for users.